SU1480139A1 - Device for synchronization of noise-like signals by a delay - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to reduce the time taken to synchronize. The synchronization device contains a matched filter 1, detector 2, threshold blocks 3 and 8, r-4 pseudo-random sequence, control unit (CU) 5, key 6 and correlator 7. The input signal simultaneously arrives at key 6 and filter 1 and further from filter 1 through detector 2 to threshold unit 3, which compares it with the first preset level. If the signal exceeds a predetermined level, a pulse signal is generated for r-4 and CU 5. R-4 produces a reference signal arriving at the correlator 7, which also receives an input signal through switch 6, controlled by CU 5. Signal The correlator of the torus 7 is compared in the threshold block 8 with the second predetermined level, and signals of exceeding or not exceeding the level are generated, which enter the control unit 5. When the level is exceeded, the control unit 5 generates a synchronization signal at the information output. If the level 5 is not exceeded, the CU 5 generates a control signal for Mr. 4. The goal is achieved by the CU 5 containing counters 9 and 12, the memory block 10 and the driver 11 of the control signals. 3 il.

Description

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The invention relates to radio engineering and can be used in radio receiving devices of broadband signals.

The purpose of the invention is to reduce the time taken to synchronize.

Fig. 1 shows the structural electrical circuit of the device for the synchronization of noise-like signals (SHNS) by delay; in fig. 2 - logical block diagram; on fig.Z - time diagrams of the device operation synchronization PSS delay;

The device synchronization device PSS delay contains a matched filter 1, detector 2, the first threshold unit 3, the generator 4 pseudo-random sequence (PSP),

control unit 5, key 6, correlator - torus 7 and second threshold unit 8,

Control block 5 comprises a first counter 9, a block of memory 10, a driver 11 of control signals and a second counter 12,

The generator 4 of the memory bandwidth contains a generator of 13 clock pulses, an additional key 14, and a driver 15 of the memory bandwidth.

Shaper 1 control signals contains a trigger 16, the element And 17, the first one-shot 18, the first counter 19f bus driver 20, the decoder 21, the second one-shot 22 to the second counter 23.

Device synchronization PSS delay works as follows. The input signal is fed simultaneously to the corresponding input of key 6 and to the input of filter 1 (TF) matched with the segment, from which the signal through detector 2 is fed to the input of the first threshold unit 3 (PB), which compares it to level P1 and in case of exceeding signal P1 generates a pulse signal (fig.Za), which simultaneously enters the input of the generator 13 clock pulses (GTI) and the information input of the control unit 5 (CU). The pulses from the output GTI 13 (fig. 36) simultaneously arrive at the clock input of the first counting ik 9, which starts the counting, and through the open additional key 14 to the input of the Lormirovat 15 SRP, which begins to produce a reference SRP, which enters the input of the correlator 7,

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to the information input of the CU 5, this block 5 at its output generates a signal (fig.Sv), which is fed to the input of the key 6, which passes the input signal to the corresponding input of the correlator 7. After a certain time required for the correlator 7 to work, it produces the signal arriving at the input of the second PB 8, which compares it with the P2 level and generates a signal of exceeding (Fig. 3e) or not exceeding (Fig. 3c), arriving at the input of control unit 5, which in case of exceeding the P2 level produces a signal at the information output on synchronicity (f ZG), and if the P2 level is not exceeded, the corresponding signal (FIG. 3) enters the input of the control signal generator 11, which extracts the corresponding control signals for the memory unit 10 and the second counter 12, which provide generating a control signal arriving at the control input of the generator i SRP, while the additional key 14 is closed for the duration of the action of the control signal, i.e., a time shift occurs in the SRP signal at the output of the imaging unit 15 by the amount determined by the number of pulses in the GTI 13, which he developed between the first and second elevations of the threshold P1 (Fig, 3m), after which the reference bandwidth again arrives at the input of the correlator 7.

The signal (Fig. 3a) simultaneously arrives at the input of the trigger 16 and at the input of the element I 17, But the first incoming pulse, the trigger 16, generates at the output a signal with the log level, 1 (FIG. 3), which simultaneously enters the input of the key 6, which opens And to the corresponding input of the element And 7, Signals (Fig. 3a), starting from the second, through the element And 17 are received in the form of control signals of the recording (Fig. 3g) to the corresponding input of block 10, and through block 18 in the form of control signals zeroing signals - to the input of the first counter 9 (fig, rear), i. the state of block 9, determined by the number of GTI pulses 13 between pulses from the output of block 3, is recorded by block 10 in accordance with the address generated by blocks 19 and 20, which is fed to the corresponding control input of block 10. In the case of

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the arrival of the non-exceedance signal to the input of block 21, blocks 22, 23 and 20 will form an address from which the block 10 to block 12 will be recorded using the control signal from the output of block 21 (Fig. 3k), and the value determining the duration of the control signal for PSP generator 4 (Fig. Zl).

Thus, a sequential check of the signals of excess III is carried out, carried out in parallel with the determination of these signals and terminated by a signal about the presence of synchronism (Fig. Зж).

Claims (1)

Invention Formula A delayed noise synchronization device containing a matched filter connected in series, a detector, a first threshold unit whose other input is the first threshold input of the device, a pseudo-random sequence generator, a correlator, a second threshold unit whose other input is the second a threshold input of the device, a control unit and a key whose signal input is the corresponding input of the device, 0 five 0 5 0 394 the information output of which is the corresponding output of the control unit, the information input of which is connected to the output of the first threshold block, while the output of the key is connected to the signal input of the correlator, characterized in that, in order to shorten the timing, the signal input of the key is combined with the input matched filter, while the control input and the clock output of the pseudo-random sequence generator are connected to the corresponding output and input of the control unit, which is designed as Then, the connected control signal generator, the first counter, the memory unit and the second counter, the clock input of which is combined with the corresponding input of the first counter and the clock input of the control unit, the information output, the input and information input of which are the corresponding outputs and inputs of the control generator signals, the control outputs of which are respectively connected to the corresponding inputs of the second counter and the memory block. I