SU1499517A1 - Phase triggering device - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve noise immunity and reduce the time of transmission and separation of the phase-start signal. The phase-start device contains on the transmitting side a block of setting 1 address, a driver of 2 pulses of variable duration, a shift register 3, a block 4 of comparison, elongates AND 5 and 7 and an RS flip-flop 6, and on the receiving side a selector 8 of pulses of variable duration, the switch 9, the shift register 10, the blocks 11 and 12 of the comparison, the pulse counter 13 and the ELs 14 and 15. The recurrent sequence formed on the transmitting side goes through the communication channel to the receiving side. Here a pulse comparison of the received and generated sequences is carried out and a signal is generated at the output of the And 14. This signal will be present in cases if the duration of the received pulses corresponds to the address of the subscriber or the circular signal, if the structures of the recurrent sequences coincide and if the signal of the end of the sequence is received. 1 il.

Description

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The invention relates to telecommunications and can be used in session communication systems for recurrent phase start.

The aim of the invention is to increase noise immunity and reduce the transmission and release time of the phase-start signal.

The drawing shows the structure on the electrical circuit of the phase start device.

The phase-start device contains on the transmitting side an address setting unit 1, a shaper of 2 pulses of variable duration, a shift register 3, a comparison block 4, the first element 5, the RS flip-flop 6, the second element 7, and on the receiving side a selector 8 of variable length pulses - efficiency, switch 9, shift register 10, first 11 and second 12 comparison blocks, counter 13 pulses, output 14 and second 15 elements I.

The phase start device works as follows.

On the transmitting side, the address setting unit 1 is set to a certain state, the corresponding address

selected subscriber. On one of the N

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the outputs of the address setting block 1 (N is the number of addresses) a signal arrives at the shaper 2, which | rm generates its own pulse when a pulse arrives, the duration of the iToporo is determined by the time parameters of the m setting elements connected (disconnected using the address setting block 1.; By the start signal RS-flip-flop 6 using the first element AND 5 of the circuit closes the feedback circuit of the register 3 (the outputs of the bits of the register 3 - block 4 of the comparison - the first element And 5 - the input of the first register bit 3). Under the action of clock pulses at the input l 2 pulses of a recurrent sequence are received. For each incoming pulse, shaper 2 generates its own pulse, the duration of which corresponds to the address of the selected subscriber, while the total duration of the recurrent sequence does not change, since it is not the total change in the duration of all pulses, but a change combinations of durations of single and zero pulses, i.e.

as far as 1 increases, O decreases and vice versa.

From the output of shaper 2, the recurrent sequence enters the communication channel. The second element And 7 analyzes the completion of the formation of the recurrent sequence. For a-bit register 3, as a signal of the end of the recurrence, you can choose a signal that there are signals 1 (or M-1) at all its outputs. At the same time, at the output of the second element, And 7, a Wits signal that will switch the RS flip-flop 6 to the initial state. Transmission of a recurrent sequence whose duration corresponds to a specific address is terminated.

At the receiving side, the input signal (from the communication channel) is fed to the selector 8, at the output of which the pulses appear only if the duration of the input pulses corresponds to the subscriber’s own address or a circular phase start. From the output of the selector 8, the input signal through the switch 9 is fed to the information input of the register 10 and the second input of the second comparison unit 12, the first input of which receives pulses of the recurrent sequence formed by the register 10, the comparison unit 12 compares the received and formed pulse sequences. When receiving a recurrent sequence, the structure of which corresponds to the structure of the sequence formed by the register 10, at the output of the block.

12 comparisons are generated coincidence pulses, which are counted by a counter 13. Upon receipt of another Q pulse coincidence pulses (the value of Q sets the threshold of the counter

13 and is selected based on the false reception probability of a code combination Q elements long) The output of the counter 13 is a signal that switches off the output of the selector 8 using the switch 9 and closes the feedback circuit of the register 10, which starts the autonomous generation of the recurrent sequence before it is selected the end of the second element

And 15. From the output of the second element And 15, the signal goes to the second input of the first element And 14, to the first input

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which the signal comes from the output of the selector 8, and to the third input from the output of the counter 13. At the output of the first element I 14, the signal is present only if the duration of the received pulses corresponds to the address of the subscriber or the circular signal, if the structures of the recurrent sequential match IQ Tei and if the end sequence signal is received ..

Claims (1)

Invention Formula A phase-start device containing, on the transmitting side P9, an RS-flip-flop connected, the first element AND and the shift register, as well as the address setting unit, the second element AND and the comparison unit, the first and second inputs of which are connected to the corresponding outputs of the shift register and the output the comparator unit is connected to the second input of the first element I, the S input of the RS flip-flop and the combined clock inputs of the shift register being the input of the Start signal and the first clock input of the device, respectively, on the receiving side the first and second comparison blocks, the pulse counter, the switch 1 and the shift register, the first and second inputs of the first comparison block are connected to the corresponding outputs of the shift register, the output of the first comparison block is connected to the first information input of the switch, and the combined clock inputs Q five 0 five about , five 17 ° the shift is a second time clock input of the device, characterized in that, in order to increase noise immunity and shorten the transmission and separation of the phase start signal, a variable-length pulse generator is inserted at the transmitting side, while the outputs of the address block are connected to the corresponding controls variable input pulse shaper, the information input of which is connected to the output of the first element And, the outputs of the register are connected to the corresponding inputs of the second element a And, the output of which is connected to the R-input of the RS-flip-flop, the output of the variable duration pulse maker is the channel output of the device, sequentially connected variable pulse selector and the first element I are entered on the receiving side, while the output of the variable pulse selector is connected to the second input of the second comparison unit and in the second information input of the switch, the outputs of the shift register nos. 1 to the corresponding inputs of the second And element, the output of which is One to the second input of the first AND gate, the third input of which is connected to the output of the pulse counter, with the pulse duration variable input selector and an output of the first AND gate are respectively the input and output channel phase starter signal.