SU1285608A2 - Interface for asynchronous ganging of asynchronous binary signals - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase accuracy. The device contains on the transmitting side a phase comparator 1, a phase coder 2, a control valve (UR) 3, a phasing combination sensor 4, a memory block 5, an initial phasing combination sensor 6, RS-triggers 7, 8, And 9 elements -11, OR 13, 14, divider 12 by N,

Description

Is3

00

sd

but:

00

33i-i- - CAC delay element

Fi & .1

14)

15 delays and a ring shift register (RED) 16, and at the receiving side — a switch, a phase phasing unit, a phase decoder, a phase-level AFC circuit, an UR, a memory unit, an initial phasing combination decoder, an RS flip-flop, an AND, OR element Cattle A synchronous binary signal, the next with a clock frequency f, is introduced into a digital communication channel, characterized by a higher carrier frequency.

one

The invention relates to telecommunications, can be used for asynchronous input-output of synchronous binary signals into digital paths of systems with pulse-code modulation, delta modulation and other digital modulation methods and is an improvement of the device according to auth.s. No. 510792.

The purpose of the invention is to improve accuracy.

FIG. 1 shows a structural electrical circuit of the transmitting side of the asynchronous interface device of synchronous binary signals in FIG. 2 is a structural electrical circuit of the receiving side of the device.

The transmitting side of the asynchronous interface of synchronous binary signals contains phase comparator 1, phase encoder 2, controlled valve 3, sensor 4 of phase combination, memory block 5, sensor 6 of initial phase combination, first 7 and second 8 RS triggers, first 9, second 10, third 11 elements And, divisor 12 by N ,. First 13 and second 14 elements OR, delay unit 15 and ring shift register 16.

. The receiving side of the asynchronous interface of synchronous binary signals contains a switch 17, a cycle phasing unit 18, a phase decoder 19, a PLL circuit 20, a controlled valve 21, a memory unit 22, an initial phasing combination decoder 23, an RS trigger 24, the And element 25, ring register 26

, using the transmitting part of the device. At the beginning of the communication session, it is necessary to phase out the reference and clock pulses in the transmitter. According to the start signal, sensor 6 through the OR 14 element transmits to the receiving side of the device a combination of an initial phasing unit with a length of N-1 elements and a phasing pulse at the Nth position. Due to this, the initial phasing of the transmitting and receiving parts is achieved. 2 Il.

five

0

five

0

five

shift, delay unit 27, element OR 28.

Asynchronous interface device of synchronous binary signals pa-. bots as follows.

Synchronous binary signal with the next frequency fj. . is introduced into a digital communication channel characterized by a higher carrier frequency fc. This operation is carried out using the transmitting part of the device proposed. At the beginning of a communication session, it is necessary to phase the reference and clock pulses in the overeating part of the device. In order to reduce the phasing time, the device performs phasing of carrier frequency pulses fc and clock frequency pulses f by first matching frequency pulse f, and frequency pulse f on the first And 9 element, which drives a single pulse to translate the first RS flip-flop 7 into one state. The moment of the first coincidence of the frequency pulses f and f is the beginning of the superframe.

A single signal from the output of the first RS flip-flop 7 triggers sensor 6, divider 12, which forms reference pulses q / N, and also allows the supply of sequences of pulses of frequencies q and fg to the device blocks through the second 10 and third 11 And elements respectively. According to the start signal, sensor 6 sequentially at frequency c through the second element OR 14 transmits to the receiving side of the device an initial phasing combination with a length of N-1 elements and a phasing pulse at the Nth position, thereby achieving the initial phasing of the transmitting and receiving parts. After transmitting the initial phasing combination, the sensor 6 is turned off by a single signal from the output of the second RS flip-flop 8, which is transferred to this state by the first reference pulse from the output of the divider 12. Divider

to the switch 17. Therefore, the phasing pulse transmitted to the receiving side after the combination of the initial phasing at the Nth position passes to the switch 17 and is sent last to the block 18. The switch 17 sends signals from the communication channel 11 -chain m, of which (n + 1) is reserved for information; 12 gives the first supporting pulse to positon impulses, and {s- (n + 1)} to

service.

The last Nth output of the switch 17 is phasing. With the help of block 18, to which the Nth is connected

The output of N pulses of frequency f at its input.

The reference pulses from the divider 12 are fed to the ring register 16

shift, which pushes forward-f5 the output of switch 17, and the controlling

the output, in turn, is connected to the shifting input of the switch 17, the i-ro output of the i-ro impulse is generated at the i-th output of the switch;

pulses. Block 18 generates a sequence of frequency reference pulses.

The pulses are in their cells, the outputs of which are connected to block 15. The reference pulses are delayed by a value of 6, corresponding to a certain transmission cycle within the superframe. The delayed reference pulses are fed to the input of the reference pulses of the phase comparator 1, which, at its main output, generates an analog signal of a time difference, between the delayed reference and the next following clock pulse.

This signal is processed by encoder 2 and recorded in a binary code in the corresponding cells of block 5. In addition, a code phasing combination code is sent to block 5 from sensor 4.

, synchronous with the reference, not delayed pulses on the transmission.

25 The decoder 19 restores the position of the pulse, which, being delayed by the appropriate value; represents the control pulse for the corresponding transmission cycle

30 within the superframe. This pulse is used to regenerate the clock frequency in circuit 20. The recovered clock frequency f is controlled by the output of circuit 20.

The information inputs of unit 5 j are junction distributor 21, which is triggered with the corresponding outputs of controlled distributor 3, the start of operation of which is determined by a pulse from the second output of phase comparator 1. The signals at outputs of control unit 40 22 are sent to subscriber line of distributor 3 to serve - consumer information. By the end of the control pulse from the output of the element OR 28.

As a result, the recovered synchronous binary signal from the output of the block

writing a synchronous binary signal (VTS) to block 5. The VTS information, service signals of encoder 2 and sensor 4 recorded in this block are read into the communication channel through the second element OR 14 by a sequence of pulses with a tracking frequency f.

At the receiving part, the decoder 23, at the beginning of the session, receives from the communication channel a combination of initial phasing with a length of N-1 elements and decodes it, as a result of which a single signal appears at its output, which flips the RS flip-flop 24 to one state, which is maintained until the end of the session. The signal from the output of the RS flip-flop 24 opens element 25 for passing information to the switch 17. Therefore, the phasing pulse transmitted to the receiving side following the combination of the initial phasing at the Nth position mutator 17 and sent last to block 18. Switch 17 directs signals from a communication channel along 11 circuits, of which (n + 1) is reserved for informational pulses, and {y- (n + 1)} - under

service.

The last Nth output of the switch 17 is phasing. With the help of block 18, to which the Nth is connected

switch output 17 and the controlling

, synchronous with the reference, not delayed pulses on the transmission.

The decoder 19 restores the position of the pulse, which, being delayed by the appropriate value; represents the control pulse for the corresponding transmission cycle

within the superframe. This pulse is used to regenerate the clock frequency in circuit 20. The recovered clock frequency f is controlled by the output of circuit 20.

22 is sent to the subscriber line to the information consumer. By the end of the control pulse from the output of the element OR 28.

As a result, the recovered synchronous binary signal from the output of the block

During the communication session, signals are sent to the first 7 and second 8 RS-triggers from the front side and to the RS-trigger 24 on the receiving side of the device, which set these elements to their initial state.

Claims (1)

Invention Formula Asynchronous interface of synchronous binary signals according to auth.St. No. 510792, which is due to the fact that, in order to improve accuracy, the first element I, the first RS trigger, the divider by N, the ring shift register, are additionally introduced on the transmitter side the delay unit and the first OR element connected in series to the second RS trigger, the sensor of the initial phasing combination and the second OR element, and also the second and third elements I. Combined by the first inputs. The first element And and are the carrier pulse, the second inputs of the first and third elements are combined and are the clock input, the R inputs of the first and second RS flip-flops are combined and are the signal input of the device Start, the S input of the second RS flip-flop is connected to the output divider by N, the combined first inputs of the second and third elements AND are connected to the input. Starting the sensor of the initial phasing combination, the carrier frequency input of which is connected to the combined output of the second element AND and the carrier input In this case, the output of the third element I is connected to the combined clock inputs of the controlled distributor and phase comparator, to another input 5 of which is connected to the output of the first OR element, and on the receiving side, the serially connected decoder of the initial phasing combination, the RS flip-flop is additionally introduced 10 and the element And, the second input and output of which are connected respectively to the input of the decoder of the combination of the initial phasing and to the corresponding input of the switch, 15 serially connected ring shift register, delay unit and IZH element, the output of which is connected to the combined input of the PLL and another controlled input, distribute 20 l, while the output of the phase decoder is connected to the input of the ring shift register, the R input of the RS flip-flop is given a signal The end of the session, the input of the decoder combination of the initial The frequency of the memory block whose phasing output is the input of the receiving unit is connected to the second input of the second side of the asynchronous matching device, OR, whose output is synchronous binary signals with the output of the transmitting side. In this case, the output of the third element I is connected to the combined clock inputs of the controlled distributor and phase comparator, to another input which is connected to the output of the first element OR, and on the receiving side the serially connected decoder of the combination of the initial phasing, RS-flip-flop is additionally introduced and the element And, the second input and output of which are connected respectively to the input of the decoder of the combination of the initial phasing and to the corresponding input of the switch, a circular shift register connected in series, a delay unit and an IL element, the output of which is connected to the combined input of the PLL circuit and another input of the controlled distributor, while to the input of the ring D