SU1552388A2 - Device for asynchronous coupling of synchronous binary signals - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve the accuracy of the matching of digital sequences. For this, the asynchronous interface of synchronous binary signals contains on the transmitting part two RS-flip-flops, an initial phase phasing combination sensor, three AND blocks, a divider by N, a ring shift register, a delay unit, a clock frequency multiplier, two EL, phase comparator, phase coder, shift register, clock interval decoder, controllable distributor, phase combination sensor, subtraction unit, fast clock pulse shaping unit and memory block, and at the receiving part the combination decoder is initial Phase Phase, RS-flip-flop, Motor I, Phase Locking Unit, Clock Interpreter, Time Clock Interpreter, Fast Clock Pulse Forming Unit, Switch, Shift Register, Ring Shift Register, Delay Unit, Memory Block, Summing Block, El OR, controllable valve, phase decoder, PLL and clock multiplier. The device according to claims 2 and 3 phyles are distinguished by the implementation of a phase coder and a phase decoder. 2 hp f-ly, 4 ill.

Description

The invention relates to telecommunications, can be used for asynchronous I / O of synchronous binary signals to digital paths of systems with pulse-code modulation, delta modulation and other digital modulation methods and is an improvement of the device according to aut. St. No. 1285608.

The purpose of the invention is to improve the accuracy of the matching of digital sequences.

FIG. Fig. 1 shows a structural electrical circuit of the transmitting part of the device; Fig. 2 - the same, the receiving part; in fig. 3 is an electrical diagram of a phase coder; in fig. 4 is an electrical circuit of a phase decoder.

The device contains the first RS-flip-flop 1, the sensor 2 of the combination of the initial phasing, the first element of the OF, the second RS-flip-flop 4, the second element And 5, a divider 6 by N, the third

SL SP N5

GO OO 00

N)

element 7, ring shift register 8, delay block 9, clock multiplier 10, first element OR 11, phase comparator 12, phase encoder 13, shift register 14, decoder 15 clock frequency interval (ITS), controllable valve 16 phasing combination, subtracting unit 18, fast clock pulse generating unit 19, memory block 20 and the second element OR 21.

In addition, a synchronous binary asynchronous interface device

By means of this signal, the second and third elements And 5 and 7 allow the channel and clock pulses to be supplied to the device blocks, respectively, and the divider 6 generates the reference pulses of the frequency Hz / N. According to the trigger signal, the sensor 2 sequentially at the frequency fH through the second element OR 21 transmits to the receiving side of the device a combination of initial phasing with a length (N-1) of elements. When received at the reception, this combination provides an initial receiver phasing and transfer

20

25

thirty

signals contains a decoder 22 combines - 15 giving parts of an interface, initial phasing, RS-flip-flop 23, element 24, a cycle phasing unit 25, a decoder 26 of the clock frequency interval (TFC), a block 27 for generating fast clock pulses, switch 28, shift register 29, ring shift register 30, delay block 31, memory block 32, summing block 33, OR 34 element, controllable distributor 35, phase decoder 36, FADP circuit 37 and clock multiplier 38 frequencies.

The phase coder contains AND 39, delay 40, binary counter 41 and AND 42.

The phase decoder comprises an RS flip-flop 43, an AND 44 element, a second delay element 45, a shift register 46, a first delay element 47, and a zero decoder 48.

The device works as follows.

A synchronous binary signal following the clock frequency is introduced into a pre-digital communication channel characterized by a higher carrier frequency fH. This operation is carried out using the transmitting part of the device proposed. At the beginning of the communication session, the R-inputs of the first and second RS-flip-flops 1 and 4 are given a signal to prepare to start the device. After that, the first element And 3 fixes the moment of coincidence of one of the channel pulses

35

45

50

what is needed to fix the start of the superframe. After transmitting the combination, sensor 2 is turned off. To do this, use the first reference pulse from the output of the divider 6, which translates the first RS flip-flop 1 into one state, and that turns off the sensor 2 with its single output signal.

Divider 6 generates the first reference pulse after the arrival of N frequency pulses at its input. The reference pulses from the divider 6 are fed into the annular shift register 8, which advances the incoming pulses through its cells, the outputs of which are connected to the inputs of block 9. The reference pulses are delayed by an amount corresponding to a certain transmission cycle within the superframe. The delayed reference pulses through the first element OR 11 arrive at the input of the reference pulses of the phase comparator 12, which at its first output generates an analog signal of the phase mismatch between the delayed reference and the next clock pulse, which is called the control pulse. The second output of phase comparator 12 contains control pulses. The analog signal of the phase mismatch is processed by encoder 13, which also receives, respectively, control pulses from phase comparator 12 to the second input, and the third input is the clock sequence from the output of multiplier 10, which increases the clock frequency ff by a factor of 2.

frequency fH with a pulse clock frequency fc and generates a single signal at its output. This signal translates the second RS flip-flop 4 into a single state, as a result of which a single device start signal is sent from the output of the RS flip-flop 4 to the sensor 2, as well as to the divider 6 and to the second and third elements And 5 and 7. To act

five

0

5 giving parts of an interface,

about 35

45

50

five

what is needed to fix the start of the superframe. After transmitting the combination, sensor 2 is turned off. To do this, use the first reference pulse from the output of the divider 6, which translates the first RS flip-flop 1 into one state, and that turns off the sensor 2 with its single output signal.

Divider 6 generates the first reference pulse after the arrival of N frequency pulses at its input. The reference pulses from the divider 6 are fed into the annular shift register 8, which advances the incoming pulses through its cells, the outputs of which are connected to the inputs of block 9. The reference pulses are delayed by an amount corresponding to a certain transmission cycle within the superframe. The delayed reference pulses through the first element OR 11 arrive at the input of the reference pulses of the phase comparator 12, which at its first output generates an analog signal of the phase mismatch between the delayed reference and the next clock pulse, which is called the control pulse. At the second output of the phase comparator 12, control pulses are present. The analog signal of the phase mismatch is processed by encoder 13, which also receives, respectively, control pulses from phase comparator 12 to the second input, and the third input is the clock sequence from the output of multiplier 10, which increases the clock frequency ff by a factor of 2.

As a result of processing the analog phase difference signal, the encoder 13 at its outputs generates a binary code combination of the phase mismatch.

Not less than 2N times the fH frequency. The differential digital signal and the sign difference signal from the output of the subtracting unit 18 are recorded in the corresponding cells of the unit 20, which are separated for service data. The same block 20 records the code combination of phasing cycles from the output of sensor 17, as well as a synchronous binary signal. To record a synchronous binary signal (VTS), the corresponding cells of block 20 use clock pulses from the outputs of the controlled distributor 16, which is triggered by a control pulse the second output of the phase comparator 12. Information is recorded in the cells of the memory block 20, read from there to the communication channel through the OR element 21 by a sequence of channel frequency pulses f c,

With the arrival of the phase mismatch signal of the conjugated sequences caused by the frequency deviation of these sequences, the binary counter 41 counts the number of frequency pulses 2 fc stacked in the interval of this phase mismatch. The obtained number in binary form in parallel through the set of elements AND 42 at the moment of arrival of the control impulse is read into register 14. After this, the control counter impulse delayed in the delayed element 40 delays the binary counter 41 to the initial (zero) state. This processing of the phase difference signal is performed at the encoder.

13 in each transmission cycle. Enrolled in register 14 binary

the phase difference group is recorded in its first half. The number of cells in this register 14 is twice the number of bits in the group from the output of the encoder 13. Therefore, in the first transmission cycle, the code group of the phase error signal occupies one half of the register cells, while the other contains zeros. Register

14 is a register with parallel writing, serial transfer and parallel reading. Signals of both halves of the register

14 are sent to subtraction unit 18, where they are subtracted in binary code. For information processing use fast clock pulses from the output of block 19, the frequency of which exceeds the channel

0

,

five

0

five

0

five

0

five

0

five

In the second transmission cycle, the processing of the error signal and the formation of the service code group is repeated with the only difference that the information from the output of the encoder 13, recorded in the first group of register cells 14, is rewritten in the second transmission cycle into its second group, and in its place information of the second transmission cycle. Comparison by block 18 of these code groups allows it to form, in the second transmission cycle, a code combination of the difference signal and the sign of the difference difference signal.

In the third transmission cycle, the first group of cells of register 14 is assigned to the mismatch information of the matching sequences in this cycle, while the second group of cells is assigned to the information of the second transmission cycle, etc. From the transmission cycle to the next transmission cycle, information of one half of register 14 is rewritten into the second half and erased only in the next cycle. In the transmission cycle, in which the phase mismatch of the conjugated sequences, due to the frequency deviation, reaches a maximum value equal to the duration of the encoded encoder 13 will be recorded in the first half of the register 14 and after processing with fast clocks all the cells of the last are zeroed with a signal from the output of the decoder 15. The decoder 15, represented by A multi-input element, And, generates a signal to reset (reset) the register 14 when a combination of the matching error interval Cf and the reference delayed frequency fH / N is received at its inputs. Thus, in the next transfer cycle, register 14 starts from the initial state.

From the communication channel, the digital information is fed to the input of the receiving part of the interface device. At the beginning of the communication session, the detector 22 receives and processes the corresponding code group of length (N-1) elements, with the result that a single signal appears at its output, which translates the RS flip-flop 23 into a single state that persists until the end of the session. A single output signal from the output of the RS flip-flop 23 opens the element

And 24 for the passage of information from the communication channel to the switch 28. The switch 28 receives a phasiruction pulse that immediately follows the initial phasing combination, i.e. at the Nth position of the front-wheel cycle. It is sent to block 25, the control output of which is connected to the shift input of the switch 28. Thanks to the signals at this input, the appearance of exactly the 1st pulse within the transmission cycle is guaranteed at the i-th output of the switch 28.

The information outputs of the switch 28 from the first to (n + 1) -th are connected to the corresponding inputs of block 32. The service outputs of the switch 28 from the (n + 2) -th to (Nl) -ft are connected to the inputs of the register 29, which is register with parallel writing and parallel reading. One part records service information about the relative phase mismatch and the sign of this discrepancy coming from the switch 28, the other stores information about the absolute value of the phase mismatch caused by the mutual deviation of the frequencies of the conjugate sequences in the previous transmission cycle, and which is updated in each transmission cycle by signals from the summing unit 33 after the service data has been processed by the latter. When a code combination is entered into the second part of the register 29, The mismatch equal to 1C, the decoder 26, similar to the decoder 15 at the time of arrival of the reference pulse, decrypts this state of the register 29 and generates a reset (reset) signal of all cells of the register 29. The service signals are recorded in the register 29 at the fast clock frequency pulses from block 27 of the BTI formation. The latter is made similarly to the same block 19, which is part of the transmitting part of the interface device. The service code group is sent from register cells 29 to summing unit 33, where, taking into account the sign bit, the code group of the phase error of the corresponding transmission cycle is determined.

The output signals from summing unit 33 are sent to decoder 36. To another input of decoder 36 from unit 25

Phasing in cycles receives a sequence of reference pulses of the frequency fH / N synchronous with the reference non-delayed pulses in the transmission. At the third input of the decoder 36 comes the tact sequence.

tf

frequency 2 fc from the output of the multiplier 38, which is similar to the multiplier 10 on the transmission.

The decoder 36 restores the position of the pulse, which, being delayed by the corresponding amount O; , is a control pulse for the corresponding transmission cycle within the superframe.

In each transmission cycle, the code combination for the absolute mismatch of conjugate sequences due to the frequency deviation fc and fn is input to the inputs of register 46, which is a clocked shift register with parallel recording. This combination is written in parallel to the cells of this register. With the arrival of the frequency reference pulse fH / N, the RS flip-flop 43 is thrown into one state and enables, through AND 44, to feed a clock sequence of frequency pulses 2 -fc to output information recorded in register 46 sequentially. At the time of the arrival of a delayed clock pulse

about with

frequency / tc after the end of the output information recorded in the register 46, the decoder 48 zero is triggered, which in its implementation is an AND element and generates a short pulse. Thereafter, with the help of a short pulse delayed by the first delay element 47, the RS flip-flop 43 is switched to the initial (zero) state. The pulse received at the output of decoder 36 is delayed by the amount of. (The corresponding transmission cycle in the superframe ah limit using the chain ring shift register 30 - block

31-element OR 34 and sent to circuit 37 for regeneration of the clock frequency and triggering of the controlled distributor 35, which is clocked by the clock frequency fc restored in the circuit of the FAGHC 37 circuit.

As a result, the recovered synchronous binary signal from the output of the block

32 is directed to the subscriber line to the information consumer. At the end of the communication session, the R input of the RS flip-flop 22 is given a signal that sets it back to its original state.

Claims (3)

1. Asynchronous interface device of synchronous binary signals according to the author. St. No. 1285608, which is such that, in order to improve the accuracy of the matching of digital sequences, the multiplier of the clock frequency, the fast clock pulse shaping unit (BTI), the decoder of the clock frequency interval ( ITS), the shift register, the subtracting unit, the outputs of the phase encoder are connected to the information recording inputs of the memory unit through the serially connected shift register and the subtraction unit, the input and output of the BTI generation unit are connected respectively to the memory carrier input and interconnected by the corresponding inputs of the subtracting unit and the shift register; another group of outputs of the register shift is connected to the ITCH decoder, the input and output of which are connected respectively to the output of the first OR element and the corresponding input of the shift register, the second and third inputs; the phase encoder is connected respectively to the second output of the phase comparator and to the output of the clock multiplier, the input of which is connected to the output of the third And element, and on the downstream side the multiplier of the clock frequency plots, block forming BTI, decoder - 40 th input of the decoder zero, output element AND is connected to the combined clock inputs of the second element AND, to the combined clock inputs of the second delay element and shift register, whose inputs are the information inputs of the phase decoder, the S input of the RS flip-flop and the second input of the AND element are respectively the control and the third the inputs of the phase decoder, the output of the zero decoder is the output of the phase decoder. torus ITCH, shift register and summing unit, information inputs of the phase decoder are connected to the switch service signal outputs via serially connected shift register and summing unit K, the outputs of which are connected to the corresponding K inputs of the shift register, another group of outputs of which is connected to the corresponding group of inputs of the ITCH decoder , output and input of reference pulses 45 50 five Q 5 0 five 0 five They are connected respectively to the first input of the shift register and to the output of the reference pulses of the phasing unit in cycles, the output of the BTI formation unit is connected to the combined clock inputs of the shift register and the summing unit, and the input of the BTI generation unit is the input of the clock frequency multiplier connected respectively to the combined clock input of the controlled distributor and the output of the PLL and to the third input of the phase decoder. 2. The device according to claim 1, characterized in that the phase encoder contains an element AND, a delay element, a binary counter and a group of elements AND whose first inputs are connected to the corresponding K outputs of the binary counter, and the second inputs are combined with the input of the delay element and are the first input of the phase coder, the outputs of the group of elements I are the outputs of the phase coder, the second and third inputs of which first and second inputs of the element I, whose output is connected to the first input of the binary counter, go to The rest of the inputs of which are connected to the multi-output output of the delay delay. 3. The device according to claim 1, 1, of which it is so that the decorator f: p contains the shift register connected in series, the decoder lule the first element back-switch, RS-flip-flop, the element I and the second delay element whose output is connected to 45 50 fie. 3 Compiled by O. Melkova. Editor A. Motyl Tekhred L. Serdyukova Proofreader M. Samborska Order 341 Circulation 577 Subscription VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 figure 1