SU1649681A1 - Device for asynchronous interfacing of digital signals - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the transmission capacity of the transmission path. The asynchronous interface of digital signals contains on the transmitter side a trigger and control unit, a controlled distributor, a memory unit, an encoder, a code converter and an asynchronous transmission interface unit, and on the receiving side is a two-unit memory detector, a controlled distributor , clock generator, start-up and control unit, asynchronous receive conjugation unit, counter and information output unit. The goal is achieved by eliminating the rate matching channel, i.e. exclusion in each cycle of transmission of single service rate matching information intervals. The device also differs in the implementation of a code converter consisting of two OR elements, two AND elements and two NOT elements.

Description

The invention relates to telecommunications and can be used for the input / output of synchronous binary signals to digital paths of systems with delta modulation and pulse code modulation.

The aim of the invention is to increase the transmission capacity of the transmission path.

FIG. Figures 1 and 2 show the structural electrical circuits of the asynchronous interface device of digital signals at the transmitting and receiving sides.

The asynchronous interface of digital signals contains on the transmitter side a starting and controlling unit (CDU) 1, a controlled distributor 2, a memory block 3, an encoder 4, a code converter 5, which includes the first and second elements OR 6 and 7 first and second

Elements 8 and 9 and the first and second elements are NOT 10 and 11, as well as an asynchronous transfer interface block (TSA) 12, and on the receiving side a detector 13, an additional detector 14, the first and second memory blocks 15 and 16, are controlled dispenser 17, clock generator 18, start-up and control unit 19, asynchronous receive interface 20, counter 21 and information output block 22

The essence of the invention consists in eliminating the velocity matching channel, i.e. in the exception in each cycle of transmission of single service rate matching information intervals,

Information on the coordination of speeds (in the prototype and this device it is information about the deviation of the number of single intervals of useful information in the cycle

About Ч Ч) About

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transmissions from the predicted number) are transmitted by combining the coding of the payload of the transmission cycle with error protection of a given multiplicity. On the transmitting side of the device, in the start-up and control unit 1, cyclic reference pulses are generated with the following frequency fH / fnN. In other words, the so-called hypercycles are organized, significantly longer than the superframes used in the prototype and containing m transmission cycles (the value of m depends on the mutual instability of the conjugate frequencies and in practice –100), i.e. cycles of such maximum length M m N, at which the influence of the instability of the conjugate frequencies does not lead to the loss of the number of useful information intervals in them compared to the prototype. In transmission cycles (length N elements), useful information is coded with error protection of a given multiplicity. In this case, if in the hypercycle the number of unit intervals of useful information does not differ from the predicted one, then the transmitting side of the device issues, in transmission cycles, allowed combinations of the selected code. If this number is different from the predicted one, then the inverse-allowed inverse combinations (forbidden combinations) are formed at the output of the transmitting side of the device in each transmission cycle. At the same time, the transition to coding a combination of one type or another is the service information on rate matching. On the receiving side of the device, allowed or prohibited combinations of transmission cycles of each hyperframe are decoded. When decoding, the original information is also restored. In this case, information is restored in one of the parallel branches in the case of coding by allowed combinations, in the other - in the case of coding by forbidden combinations. At the regenerated frequency, the information decoded in the branch where less errors were detected is output.

The asynchronous interface of digital signals operates as follows.

A synchronous binary signal following the clock frequency fc is introduced into a digital communication channel characterized by the frequency fn of the carrier sequence. The device starts working on the transmission by the moment of coincidence of the clock pulse of the frequency fH / N, where N is the length of the transmission cycle, in the start-up and control unit 1, at one of the outputs of which

reference pulses with the following frequency fH / m N in accordance with a given length of the M N m hypercycle.

After switching on the device chipboard unit

12 is zeroed and then begins to work on the first reference frequency pulse fH / mN. This ensures the operation of the device, starting with the first information cycle of each superframe. The counting of subsequent information cycles within each superframe is carried out by reference pulses.

The actual number of elements in the information cycle may differ from the predicted one due to the relative frequency deviation fc and tn or due to the constant phase shift of the actual and predicted sequences. According to the deviation information

0 the number of elements in the information cycle from the predicted block TSA 12 generates a single signal on one of three outputs connected to the inputs of the element OR-6 of the converter 5 code. At the same time

5, the other two outputs are zero signals. The signals on the specified outputs of the block АСП 12 carry one of the following commands: subtract one element from the predicted number of elements in

0 information cycle; add one element (logical / july) to the predicted number of elements in the information cycle; add one element (logical unit) to the predicted

5 number of elements in the information cycle,

These commands are combined through the element OR 6, at the output of which a single signal appears in any case deviating the number of single information intervals of useful information in the information cycle from the predicted number.

The reference pulses from the output of the block

5, the start and control 1 starts the control valve 2, which is clocked by the clock frequency pulses fc. Using the controlled distributor 2, information is recorded in a block

0 memory 3, having (n + 1) cells. The information part of the transmission cycle (the length of the transmission cycle N (n + 1) / m elements) is read from memory block 3 into encoder 4 with fast clock pulses (BTI), which are formed 5 in start-up and control unit 1. At the same time, their frequency exceeds the channel frequency tn not less than 2 N + s times, where S is redundancy, is necessary to encode information of transmission cycles with error protection of a given multiplicity K.

By operating the BTI in encoder 4, pseudo-random sequence (PSP) combinations are formed, corresponding to information of the transmission cycle, whose length is N elements, and having redundancy S, necessary to encode information with error protection of a given multiplicity K.

From the output of encoder 4, at the carrier frequency H, the combinations arrive at the inputs of the first element AND 8 and the second element NOT 11 of the converter 5 of the code; from the output of the element 11, the inverted combinations arrive at the input of the second element AND 9. Signals at the output of the transmitting part of the device appear on output element OR 7, combining signals from either the output element AND 8, or from the output element AND 9 depending on the presence of a signal at other inputs of elements AND 8 and 9. Signals at these inputs (signals about the deviation of the number of information intervals from the predicted th) are mutually reversible and are direct and inverted elements NOT 10 signals from the output of the element OR 6. As a result, the output of the device produces allowed or forbidden combinations in the transmission cycles of each hypercycle, depending on whether there is a deviation of the actual number of intervals in the information cycle from the predicted numbers or not.

On the receiving side of the device, the memory bandwidth is processed in parallel in decoders 13 and 14. Before the start of a communication session, a service code is formed on the transmission side — a memory bandwidth of N + S elements (corresponding to the information combination consisting of zeros from the zeroed memory block). 3). In this section, the memory bandwidth received by the decoder 13 in the start-up and control unit 19 is the initial phasing of the reference pulses of the receiving and transmitting sides of the device, which allows prediction both at the reception and at the transmission in phase. After that, the start-up and control unit 19 begins to generate pulses of the frequency fH / N and fast clock pulses. In decoders 13 and 14, decoding occurs with the detection and correction of errors of a given multiplicity K, both for the case of encoding information by allowed combinations, and for the case of encoding by forbidden combinations.

The signals of the presence of discrepancies (errors) come from the output of the decoder 13 to the input of the counter 21, in which the number of transmission cycles with errors in the hyperframe is counted when decoding the allowed combinations. If this number

equal to (t / 2 + 1), then a single signal is generated at the output of the counter 21, which serves as an indication that the information that is recovered in another branch, i.e. in the decoder 14.

The transmission cycle information recovered during forward and reverse decoding from the outputs of the decoders 13 and 14 are recorded in memory blocks 15 and 16. Information from one or another memory block (15 and 16) is read at a regenerated clock frequency depending on the presence of the output signal of the counter 21, which is fed to the control input

5 of the information output block 22, to the other inputs of which the readable information is received from the memory blocks 15 and 16.

The nominal frequency of the generator 18 clock frequency corresponds to the case when the information cycle contains n elements. In the case when (n + 1) or (n - 1) elements are actually contained in the information cycle, the asynchronous receive conjugation unit 20 forms the signal for a corresponding increase or decrease in the clock frequency relative to its nominal value.

The control valve 17 is started by reference pulses from the output

0 of the starting and controlling unit 19, and is clocked by the regenerated clock frequency coming from the output of the 18 clock frequency generator. With the help of a controlled distributor 17 of the memory blocks 15 and 16 through

5, the information output block 22 reads the recovered synchronous binary signal.

Claims (2)

1. An asynchronous interface of digital signals containing a serially connected controllable distributor, a memory block, an encoder and a code converter on the transmitting side, the control inputs of which are connected to the control command outputs of the asynchronous transmission interface; another memory unit output and clock signal outputs, reference pulses and 0 fast clock pulses of the start-up and control unit, the output of the signal frequency channel of which is connected to the first control input of the encoder, to the second control input of which the output is connected 5 fast clock pulses of the start-up and control unit, which is connected to the corresponding input of the memory unit, and the output of the signal of the clock frequency and the output are connected to the control inputs of the controlled distributor reference pulses of the start-up and control unit, and at the receiving side - serially connected decoder and memory unit, to the recording inputs of which through a controlled distributor the output of the clock frequency generator is connected, to the control inputs of which the corresponding outputs of the asynchronous reception interface are connected, to the control the input inputs of which are connected respectively to the output of the reference pulses and the output of the fast clock pulses of the starting and control unit, which is connected to the corresponding input of the detector, another output D which is connected to the input of the start-up and control unit, the output of the reference pulses of which is connected to another input of the controlled distributor, characterized in that, in order to increase the capacity of the transmission path, an additional detector, an additional memory block and a block are introduced at the receiving side information output, as well as a counter, while the additional detector output is connected via a counter to the control inputs of the asynchronous reception and output information block, to another at the entrance 0 the output of the memory block is connected, the recording inputs of which are connected to the corresponding inputs of the additional memory block, the information input of the decoder is connected to the corresponding input of the additional detector, to the control inputs of which the output of the fast clock pulses and the auxiliary output of the reference pulses of the launch and control unit are connected, which is connected to the corresponding input of the decoder. 2. Device pop. 1, characterized in that the code converter is made in the form of serially connected first element OR, first element NOT, first element AND, second element OR, to the other input of which the output of the first element OR is connected through the second element And, to the other input of which is connected the output of the second element NOT, the input of which is connected to the other input of the first element AND, and is the input of the code converter, the control inputs and output of which are the three inputs of the first element OR and the output of the second element Enta OR. N 3 &