SU1283977A1 - Coding device - Google Patents

Abstract

The invention relates to computing technology, namely, information and measuring devices, and is intended to encode information transmitted over various communication channels in a serial form. The encoder allows not only to control the parity (oddness) of the number of units in the code message, but also to control it additionally. the constancy of the number of pulses, which provides increased noise immunity. In addition, reducing the duration of the code message in the device provides an increase in its speed. The coding device contains a clock pulse generator, three keys, the AND element, the UNEMINABILITY element, two triggers, a decoder, two multiplexers, two pulse counters, and a shift register. 2 Il. O (L

Description

The invention relates to computing, namely, information and measuring devices, and is intended to encode information transmitted via various communication channels in a sequential form.

The purpose of the invention is to increase the speed by reducing the duration of the code message and increasing the noise immunity by controlling a constant number of pulses.

Figure 1 shows the functionals (periods) in the code parcel. Zero at the output of the trigger 8 prohibits the shift of inorption in the shift register 14 and allows the output to the output of the multiplexer 10 of the pulse of the code send generated at the first output of the decoder 9 and then coming through the multiplexer 1 to the output 17 of the device. After the first two periods of the code parcel (the start of the code parcel) the pulse from the output of the first bit, the counter 13 sets the trigger 8 to one, thereby allowing the passage

on the coding scheme; on

FIG. 2 shows timing diagrams, explaining to the output of multiplexer 10 which have its operation. The pulse of the first information section The control signal contains a generator T of clock pulses, the first

a number of code send from one of you, the decoder moves 9, corresponding to the two highest bits of the input information 20, located in the highest rows of register 14, At the end of the current period (the first information bit) the code to send impulses from the counter output 12 translates the state of trigger 7 when one 1 is present in the input information bits under consideration and the information in register 14 is shifted by two bits in the direction of increasing their weight.

2 key, Ifl element 3, second and third keys 4 and 5, element 6 UNEMATICAL, first and second triggers 7 and 8, descrambler 9, first and second multiplexers 10 and 11, first and second 1s cheaters 12 and 13 pulses and shift register 14, input 15 Start, information input 16 and output 17 ..

2

a number of code parcels from one of the outputs of the decoder 9, corresponding to the two most significant bits of the input information, which are in the highest bits of register 14, At the end of the current period (the first information bit) the code message impulses from the output counter 12 switches the state of trigger 7 when one 1 is present in the input information bits under consideration and the information in register 14 is shifted by two bits in the direction of increasing their weight.

Figure 2 shows the following notation: a is the input signal 15

 b - signal at the first output; Then, the formation of a second counter of 13 pulses begins; c - signal for the first information bit of the device code output 17; g - signal at the output of the key 4; d - signal on the first

parcels, etc. until the end of the penultimate information bit, when the output element And 3

the output of the counter 12 pulses; e

Rows (periods) in the code parcel. Zero at the output of the trigger 8 prohibits the shift of information in the shift register 14 and resolves the arrival at the output of the multiplexer 10 of the pulse of the beginning of the code parcel generated by the first output of the decoder 9 and coming further through the multiplexer 11 at the output 17 of the device. After the first two periods of the code parcel (the start of the code parcel) the pulse from the output of the first bit of the counter 13 sets the trigger 8 to one, thereby permitting the passer-by and the code parcel from one of the decoder outputs 9 corresponding to the two most significant bits of the input information in the high bits of register 14. At the end of the current period (the first information bit) of the code message, the pulse from the output of counter 12 switches the state of trigger 7 if there is one 1 in rows x bits of the input information and shift information in the register 14 in two bits in the direction of increasing their weight.

Then the formation of the second information bit of the code code begins.

Then the formation of the second information bit of the code code begins.

parcels, etc. until the end of the penultimate information bit, when the output element And 3

the output signal of the trigger 8; g - sig-35, a single potential appears on the first output of the decoder 9; 3 - the signal at the second input of the decoder 9; and - m - signals on the second you move the decoder 9; n - signal to

Determining the last bit of the code parcel (the last bit of the input information plus the digit of the control). During the last discharge code

trigger output 7 ;. about - a signal to you - 40 parcels to the output 17 of the device in the input of the element FROM,

The encoder works as follows

Upon arrival at the input signal 15

One hundred signals from the output of multiplexer 10 receive one of the signals from the output of the decoder 9, corresponding to one of the states input to the shift register 14 from the input 45, 00, 01, 10 or 11)

and determined by the states of the high bit of the shift register 14 (the last bit of the input information), and trigger 7 even or odd 50 number 1 in (t - 1) -m first bits ha - bit code parcel, respectively, 00, 01 , 1.1 and 10 At the end of the last digit of code 16, the information to be encoded is entered, and counters 12 and 13 and triggers 7 and 8 are reset to zero. Setting zero of the last digit of counter 13 leads to opening of key 4 and allowing information to arrive at output 17 devices. Clock pulses with generator 1 output through open

The last parcel of the last parcel is the key 4 and is fed to the input of the counter 12, 55 and 13; 13 is set to 1, prohibiting the duration of the period.

to the input of the counter 12 and information on the output 17 of the device to the next I signal Start.

code package ,. The overflow pulses of the counter 12 are fed to the input of the counter 13, which determines the number discerning the last bit of the code parcel (the last bit of the input information plus the control bit). During the last discharge code

One hundred of information from the output of multiplexer 10 receives one of the signals from the output of the decoder 9, corresponding to one of the input information states (00, 01, 10 or 11)

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Claims (1)

Invention Formula An encoder comprising a clock pulse generator, a first key and an AND element, characterized in that in order to increase speed by reducing the length of the code message and increasing noise immunity by controlling a constant number of pulses, the second and third keys, the UNEQUALITY element, triggers, decoder, multiplexers, pulse counters and shift register, the first output of which is connected to the first inputs of the first and second multiplexers and to the first input of the element NEVER Tb, the output of which is connected to the first input of the first key, the second output of the shift register is connected to the second inputs of the first multiplexer and the UNEQUALITY element, the output of the clock generator is connected to the first input of the second key, the output of which is connected 25 pulses, the first output of which is connected to the information input of the second pulse counter, with the first input of the third key and with the second input of the first key, the output of which is connected to the synchronization input of the first a rigger whose output is connected to a second input of the second multi 20 thirty It is united with the third input of the first mu | typlexer and with the second input of the third key, the output of which is connected by a shift input of the shift register, the second outputs of the first pulse counter are connected to the corresponding first inputs of the decoder, the first output of which is connected to the quarter input of the first multiplex output which is connected to the third house of the second multiplexer, the second outputs of the decoder are connected to the corresponding fifth inputs of the first multiplexer and the fourth inputs of the second multiplexer, the output element And is connected the first input of the second multiplexer, the first output of the second pulse counter is connected to the sixth input of the second multiplexer and the second input of the second key; the second outputs of the second pulse counter are connected to the inputs of the And element; the input of the second trigger input .1 is combined with the second input the decoder and connected to one and second outputs of the second pulse counter, the installation inputs, in the O. first and second triggers, the first second pulse counters and the input of the shift register are combined and connected to the input of the Start device; nformatsionnye vhodysdvigo th register are home device information, the second multi yield plexor, the output of the second copor 35 trigger is the output of the device. five 0 single with the third input of the first multiplexer and with the second input of the third key, the output of which is connected with the shift input of the shift register, the second outputs of the first pulse counter are connected with the corresponding first inputs of the decoder, the first output of which is connected with the quarter input of the first multiplexer, the output of which is connected to the third input of the second multiplexer, the second outputs of the decoder are connected to the corresponding fifth inputs of the first multiplexer and the fourth inputs of the second multiplexer, output e The AND terminal is connected to the fifth input of the second multiplexer, the first output of the second pulse counter is connected to the sixth input of the second multiplexer ™ and the second input of the second key, the second outputs of the second pulse counter are connected to the inputs of the I element, the installation input in .1 of the second trigger combined with the second input of the decoder and connected to one of the second outputs of the second pulse counter, the installation inputs, in the O. first and second triggers, the first and second pulse counters and the input of the shift register are combined and dineny Pu.sk to the input device, information vhodysdvigovogo register are data input devices, output of the second multiplekI LA G P "3 ka" about tv ni x e: s 5; i: c: i