SU640447A1 - Discrete signal receiver - Google Patents

Description

the input of the first element P1LI, and the outputs of the decision block, corresponding to even single and zero characters of the code combination, through the third additional element OR are connected to the input of the automatic gain control unit, in addition, the outputs of the third and fourth pulse formers through series-connected element and fifth pulses are connected to the input of the second counter.

FIG. Figure 1 shows the structural electrical circuit of the proposed device; in fig. 2 - diagrams explaining his work.

The device for receiving discrete signals contains a decisive unit 1, the control input of which is connected to the automatic amplifier control unit 2, the first element OR 3, the first counter 4 and the decoder 5, which is connected to another input of the shift register 6, are connected to the other two inputs which are connected respectively the first input and output of the first element OR 3, and the second counter 7, the output of which is connected to the input "Setting the zero of the first counter 4 and the second counter 7 and to one of the inputs of the second IL element And 8, to the other input of which the output of the first counter 4 is connected, and the output of the second element OR 8 is connected to the read input of the shift register 6, five shapers 9-13 pulses, three additional elements OR 14-16, OR-NOT element 17, with In this case, the outputs of the deciding unit 1 corresponding to odd and even zero symbols of the code combination, respectively, through the first 9 and third 11 pulse drivers are connected to the inputs of the first additional element OR 14, the output of which is connected to the second input of the first element OR 3, the outputs unit 1, corresponding to odd and even single characters of a combination of code, connected respectively through the second 10 and fourth 12 pulse shapers to the inputs of the second additional element OR 15, the output of which is connected to the first input of the first element OR 3, and the outputs of the decision block 1 corresponding to even single and zero symbols of the code combination, through the third additional element OR 16 is connected to the input of the automatic gain control unit 2, in addition, the outputs of the third 11 and fourth 12 form firs pulses through series-connected OR-NO element 17, and a fifth pulse shaper 13 connected to the input of the second counter 7.

The device works as follows.

The clock pulses allocated by the decision block 1, corresponding to the symbols "Ou," "0h," 1h (Fig. 2a-d), are compressed by the following: M | And 10-12 pulses to a duration approximately equal to half of the clock interval (Fig. 2e, e, ok, h). Compressed pulses from the outputs of the formers 9, 11 pulses (Fig. 2 d, g), arriving at the element OR 14, at its output form a sequence of zero symbols of the code word. Similarly, the compressed pulses from the outputs of the formers of 10, 12 pulses (Fig. 2 e, h), the entry element OR 15, form at its output a sequence of single characters of the code word. The sequence of compressed imiulso. Even-numbered symbols (Fig. 2, c, d), arriving at an OR-NOT 17 element, forms at its output a periodic sequence of pulses with a frequency equal to half the clock frequency, from which the driver of 13 pulses forms sync pulses shifted relative to binary codeword pulses at half the clock interval. The highlighted symbols "O and" 1 (Fig. 2 and, k) are recorded in shift register 6 and fed to the counting input of the first counter 4 to perform a check for the completeness of bits in the code-box 1. The information shift in the shift register 6 is carried out by the information itself delayed in the element OR 3. The allocated sync symbols (Fig. 2 l) are fed to the counting input of the second counter 7. The shift register 6 is shifted and cleared by filling the first counter 4 or by filling the second counter 7, which provides word synchronization in the event of insertions and precipitations at odd positions of the code word. Zeroing checks the control characters of the code word and decides whether the word can be sent for execution.

The symbols shown in FIG. 2 b and d are used to transmit code word symbols at even positions, and the symbols shown in FIG. 2 a and b are used only to transmit odd codeword positions. This structure of the code word, as well as the use of formers of 9-12 pulses at the output of decision block 1, providing compression of both odd and even characters, makes it possible to eliminate the possibility of fading of the corresponding pulses when a series of identical symbols appear in the code word, i.e. allow to provide clock synchronization in the proposed device with a technical transfer rate equal to the value of the clock frequency without using a special clock synchronization circuit with a clock generator asthoty. Use an even-numbered sequence

characters, the number of which in the code word is “empty”, allows to select a periodic sequence of pulses, which ensures word sync.

The reliability of the registration at the same clock speed as the prototype increases due to the fact that with the synchronization logic unchanged according to the words, the number of clock pulses per codeword is halved. A further increase in the reliability of registration can be obtained if the technical transmission rate is the same as that of the prototype, since, in the proposed device, the clock frequency is reduced twice, the transmission block of the decision block decreases, the energy per signal increases, the signal ratio increases / noise at the input of the decision block.

Claims (1)

Invention Formula A device for receiving discrete signals, containing a decisive unit, to the control input of which the automatic gain control unit is connected, the first OR element, the first counter and decoder: p, the output of the register of the dual register, to the other two inputs and connected, are connected to the other input the first input and output of the first element R1LI, n the second counter, the output of which is connected to the input "Setting the zero of the first counter and the second counter and to one of the inputs of the second element OR, to the other input of which is connected to the output of the first counter, and the output: the third element of the ILI is connected to the input of the sdziga register, characterized in that, in order to improve the reception performance of discrete information, enter into it five forms of pulse drivers, three additional elements OR, element OR-NOT, with the outputs of the decision block corresponding to odd and even zero c; code combination, respectively, through and the third form of rotate; 1 1 pulses are connected to the inputs of the first complement of the OR element, the output of which is connected to the second input of the first OR element, the outputs of the decision block corresponding to the odd and even 1 code symbols, are correspondingly connected through the second and fourth pulse shapers to the inputs of the second additional element OR, the output of which is connected to the first input of the first element OR, and the outputs of the decision block corresponding to even single and to the zero characters; one combination 1И, through the third additional element OR is connected to the input of the unit; automatic control of the gain, optionally, the outputs of the third 1 of the fourth pulse shapers through the successive element OR-Fifth pulse generator to the input of the second count 1k . Source NfOrma II, pr n thousand in the case of the exporter 1. The author's testimony of the USSR No. 400046, cl. H 04L 7/10, 1974. -J-l- --J P ri