SU506133A1 - Binary signaling equipment - Google Patents

Description

the yV decoders 5, to the inputs of which a linear signal 6 is connected, are fed through an NR adapter 7, controlled by a corresponding clock generator 8, each pair n − 1 clock inputs of encoders and decoders are paralleled and connected to the same outputs of the corresponding clock pulse 4 and eight.

Encoder 1 is made in the form of a 1-stage shift register li (Fig. 2), the installation inputs of the first stages and the shift input of which are connected to the like outputs n to the n-1st input of the n-bit valve 2, respectively. In addition, the input of the shift register is connected to the "-th input of the n-rant dppt bhpl directly and to its control input — through the pulse edge detection detector b, and on the l-1 inputs / r-dp-fan the corresponding clock pulses are given . The decoder 5 is made in the form of serially connected n -f-I-cascade shift register 5i, logic reset circuit 62 and trigger 5z. The outputs of the last n stages of the shift register 5i are connected to the first group of inputs of the comparison circuit 54, the output of which is connected to the control input of the logic reset circuit 62. Its output, in turn, is connected to the setting inputs of the last and the stages of the shift register 5i, and The 1 inputs of another group of the comparison circuit are supplied with the corresponding clock pulses, the inverse output of the flip-flop 5z is connected to its n-th input, the a / g- 1st input is connected to the shift input of the shift register.

The device works as follows.

In the static state, the input of one of the L encoders receives one of two voltage levels corresponding to a logical "zero or" one. Detector 1z in this case produces a pulse at its output, which opens the gate b, and logical states are recorded in the first register cells, the first of which indicates the type of the front, and the next two indicate the distance from the front to the moment of information shift in the register li. The code combination formed in the li register is output in a sequential code to the distributor 3, where all the code combinations from other encoders are combined. The combined combinations are converted in transmitter 2 into a form suitable for transmission, and are transmitted in a converted form over a communication link. At the receiving end, a linear signal containing the combined code combinations enters the linear signal receiver 6, where it is converted, after which the distributor 7 distributes it in L directions over the number of decoders.

When code combinations are promoted and the register 5i, a state occurs when the first

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the code information symbol occupies n -} - Bbiii bit of this register. In this case, the sigpals on the n inputs of the circuit. We 5.i coincide with those recorded in the cells of the register 5i.

As a result, the comparison circuit 64 generates a signal at its output, but to which the logic reset circuit 52 transfers the trigger BZ to another state and resets 2 - n bits of the register 5i, after which all bits of the register 5i and the trigger 5h are brought to the same state corresponding to the new state of information binary signals.

Claims (3)

1. Binary sigpal transmission equipment over a duplex communication line, containing transmission pa of L coders whose outputs are connected to the transmitter input, a linear signal through a transmission distributor controlled by a clock driver, and N decoders at the inputs controlled by A corresponding line signal receiver is connected to the corresponding clock form / 1em, characterized in that, in order to simplify the circuit, each pair of n-1 clock inputs (n is the length of the code combination) of both the encoders and decoders are paralleled by the corresponding shapers clock pulses. 2. Equipment according to claim 1, characterized in that the encoder is made in the form of a 1-stage shift register, the installation inputs of the first n stages and the shift input of which are connected to the single-output outputs and to the first-input input of the L-discharge valve, respectively besides, the input of the shift register is connected to the n-th input of the l-discharge gate directly and to its control input - through the pulse edge detection detector, and the cash - 1 input of the l-bit The valve is supplied with the appropriate clock pulses. 3. Apparatus according to claim 1, characterized in that the decoder is made in the form of serially connected l -} - 1-stage shift register, logic reset circuit and trigger, in addition, the outputs of the last l stage shift register are connected to the first group of circuit inputs comparison, the output of which is connected to the control input of the circuit logical reset, the output of which, in turn, is connected to the setup inputs of the last l stages of the shift register, and the corresponding clock pulses are fed to the l-1 inputs of another group of the comparison circuit, the inverse output of the trigger is connected to its l-input, al- 1 The new input is a connect with a shift input on the shift register. on the line - “ZZ -i to line1 / silsie N- N J -n whether Tantod signals 2