SU1179317A1 - Device for sorting numbers - Google Patents

Abstract

A DEVICE FOR SORTING NUMBERS containing input counters, output counter, group of elements OR, group of pulse formers, group of output elements AND, group of prohibiting elements AND, element OR, input element AND whose first input is connected to the input of clock pulses of the device, and output is connected to the summing input of the output counter and the first inputs of the prohibiting elements AND groups, the outputs of which are connected to the subtractive inputs of the corresponding input counters, the outputs of which are bitwise connected to the input m of the corresponding elements of the OR group, the outputs of the KOTopbtx are connected to the inputs of the corresponding pulse shapers of the group, the second inputs of the corresponding inhibitory elements AND of the group and the corresponding inputs of the OR element, the outputs of the output counter are bitwise connected to the information inputs of the output elements AND of the group whose outputs are informational Outputs of the device, characterized in that, in order to increase reliability when sorting equal numbers, the first and second triggers, the register, The co-owner of the number of units in the binary code, the counter of equal numbers, the first and second elements of the CID-NOT, the first and second elements AND, the reset pulse shaper, the delay element, and the outputs of the group of drivers of the group are connected to the corresponding bits of the register, the outputs of which bits are connected with the inputs of the first OR-NOT element and with the corresponding inputs of the converter of the number of units into binary code, the outputs of which are connected to the corresponding information inputs of the counter of equal numbers, the outputs of which are C are united with the inputs of the second element OR — NOT, the output of which is connected via the reset pulse shaper to the clock input of the first trigger and the inputs of resetting the register to the zero state and the second trigger, whose information input is connected to the logical input. units of the device, the inverse output of the second trigger is connected to the first input of the first element AND, the second input of which is connected to the output of the first element OR NOT and through the delay element to the second input of the input element AND, the third input of which is connected to the direct output, the first trigger, the information input of which is connected to the output of the OR element, the input clock of the device is connected to the third input of the first element AND and the first input of the second element AND, the second input of which is connected to the direct output of the second trigger and

Description

the output is the output of the resolution the output of the resolution of the recording of which is supplied and connected to the control inputs is connected to the output of the first element AND and the output elements AND of the group and subtracting the synchronization input of the second to the trigger inputs of the counter of equal numbers, gera.

1179317

The invention relates to computing and can be used in signal processing devices, communication systems, etc.

The purpose of the invention is to increase the reliability when sorting equal numbers.

Figure 1 shows the functional diagram of the device; figure 2 - timing diagram of the operation of the elements of the device.

A table of the state of the outputs of the converter of the number of units into a binary code depending on the state of its inputs (for example, five inputs) is given in Table 1.

The device contains input counters 1, ..., 1jj, output counter 2, a group of elements OR 3j,, 3j, an element OR 4, a trigger 5, a group of prohibiting elements AND 6, ..., 6, an input element And 7, a group output elements And 8, ..., 8, a group of drivers 9j, ..., 9m pulses, register 10, element W-NOT 11, element 12 delay, element And 13, trigger 14, the Converter 15 number of units in binary code, a counter of 16 equal numbers, an OR-NOT 17 element, an AND 18 element, a reset pulse shaper 19 clock input 20 of the device, information outputs 21 of the device, output 22 of resolution.

The purpose of the elements of the device is as follows. The counters Ij, .. “, 1 serve to temporarily memorize the original sorted numbers. The OR 3 elements (, ..., 3 are used to record the zero state of the corresponding counter 1, ...,, and with the zero content of the counter 1, .. ,, 1 at the output of the corresponding element OR -3, ..., 3 - zero potential. Output counter 2 is used to form a code on the device outputs 21 when sorting numbers. Element ШШ 4 and trigger 5 are used for

fixing the zero state of all the counters 1 ,, ..., IP, at the end of the sorting and generating the inhibitory potential at the second input of the And 7 element to further block the clock pulses. The formers 9 ,, ..., and register 10 are used to record the number of counters 1 ,, ..., Iff ,, set to the zero state in the last cycle. Converter 15 serves to convert the number of set bits of register 10 to a single state into a binary code (Table 1). A counter of 16 equal numbers serves to count the clock pulses produced by the device. Element ШШ-НЕ 17 serves to record the zero state of counter 16. Element And 13 and element OR-HE 11 serve to generate a signal for rewriting information from the outputs of converter 15 into counter 16 of equal numbers and setting trigger 14 to one. The first and second inputs of the And 13 element are inverted to the incoming signals. On the synchronous input of the trigger 14, the input signal is inverted. Element And 18 serves to generate a clock signal at the second output of the device and subtractive pulses for a counter of 16 equal numbers. The delay element 12 serves to ensure stable rewriting of information in the register 10 by delaying the prohibition signal on the third input of the input element AND 7 after the operation of the first element OR-NOT 11 (occurrence of zero potential), and the delay (ggAf element 12 is selected, for example, from the ratio ZeaAg - 2 7 the duration of the clock pulse Shaper 19 serves to form a signal that the second trigger 14 is set to zero, the register 10 and the clock signal for the first trigger 5, and the output signal is Either 19 is delayed relative to the leading edge of a single signal from the output of the element OR-NOT 17 for a time "Z2" which is determined, for example, based on the stable operation of the device from the ratio l l / TLI l 2 aAg b The time intervals between clock pulses are, for example, , / EDG The device elements can be, for example, the following: Counters, triggers, register, AND, OR, OR NOT elements, AND groups of elements are typical, for example, for digital TTL series 133 integrated circuits, K155, 130, K131, 530, K531, K555. Transformer 15 is implemented, for example, on the basis of typical logical elements, taking into account the state table. The shapers 9 ,,, .., 9 19 can be implemented, for example, on the basis of typical K155AGZ shapers, taking into account the functioning logic and temporal parameters given in the application materials. The device works as follows. The input counters 1; ,, ..., 1fr) bring sorts of numbers to be sorted. The registers 10 and the counter 16 are set to zero, the trigger 14 is set to the zero state, while the inverse output of the latter is the potential of a logical unit. The trigger 5 is set to a single state, while from its output to the second input element And 7 enters a single potential (initial setup circuit elements of the device in figure 1 are not shown). In the initial state, the outputs of the elements SHSh-HE 11 and 17 are unit potentials, since the register 10 and the counter 16 are zeroed, and at the outputs of the elements OR 3 ..., the unit potentials, since the contents are not equal to the counters 1 but O, and therefore, To the first inputs of the group of prohibiting elements I 6 "., ..., 6 (and the second and third inputs of the element I 7 are given resolving unit potentials. The input pulses 20 are supplied with clock pulses (Fig. 2a), which, through the element I 7 arrive at the summing input of the output counter 2 and through the group of elements And 6., ..., 6 to Calculation of the inputs of counters 1, ..., 1. At the same time, the contents of the counters 1, ..., 1 decrease and the output counter 2 increases. When the number of clock pulses corresponding to the minimum number (or several numbers) arrives at device input 20 of the sorted numbers in the counters 1., ..., 1, the contents of the corresponding counter 1 (or several counters 1, i) in which (in which) the minimum number was written, becomes equal. At the output of the corresponding elements OR 3, a zero potential appears (Fig. 25), covering the corresponding elements of AND 6 of the group, blocking the further arrival of the subtractive pulses at the inputs of those counters 1 | in which the content became equal to O. At the outputs of the formers 9 connected to Those elements OR 3, on which a zero potential was set, will have write pulses 1 in register 10 (FIG. 2d), and the number of recorded 1 for all bits of register 10 corresponds to the number of counters 1 set to zero. The element SHS-NOT 11 is triggered, the output of which exposes a zero potential. Next, the delay element 12 is triggered and on the third, the input element And 7 sets a prohibiting zero potential, according to which the arrival of clock pulses on the element And 7 is blocked (Fig. At the end of the clock pulse the element And 13 triggers, at the output of which pulse of rewriting the binary code of a number, for example, 3, set to the zero state of counters 1, to the counter 16 equal numbers according to its synchronous input (Fig. 2e). At the end of the rewriting signal (since the synchronous input of the trigger 14 inverts the signal) trigger 14 is set to one, so that from its inverse output to the third input of the element And 13 prohibits, and from its direct output to the second input of the element 18 And the resolution (figure 2) .On the output of the element OR NOT 17 is set to zero potential.The clock pulse from the first input element And 18 is fed to its output

(fig.2 and later - to the subtracting input of the counter 16, to the second inputs of the element group I B, 8, and to the second output 22 of the device. In this case, from the output of the counter 2, the output 21 of the device receives the code of the minimum number (numbers). The next clock pulse also comes from the output of the element AND 18 strobe-pulse sent to the output 21 of the device of the same content of counter 2 (FIG. 2 "). Since the number 16 was recorded in counter 16, 18 of the third subtractive pulse, the counter 16 is set to the zero state, the second is triggered. the swarm element WI-NOT 17 and at its output exposes a single potential Fig. 2i). Thus, the output of 21 devices receives the code of minimum numbers as many times as were recorded in counters 1 ,, ..., of equal numbers.

On the leading edge () of the signal from the output of the OR-NOT 17 element, the shaper 19 is triggered through the output of which a pulse appears (Fig. 2, on which the trigger 14 is reset to the ZERO state and the trigger 5 is set to the same state as at the output of the second element OR 4, the signal from which arrives at the information D input of the trigger 5. Since not all the counters 1, ..., 1 are reset in the first cycle of the device, then at some inputs of the element OR 4 there are unit potentials and output the latter is also a single potential. Trigger 5 on it shall not be

changes according to the sync pulse from the output of the former 19 of its state (single).

According to the next clock pulse, the next cycle of determining the numbers following the rank after the minimum in order of increasing begins. The cycle repeats as before: the number of installed counters 1 is determined

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the left state in the last cycle, and then the output 21 receives the code of these numbers from the output of counter 2 as many times. Moreover, the codes are accompanied by clock pulses from the output 22 of the device. The sorting cycles are repeated until all the recorded numbers in the counters 1, ..., 1 f are sorted, i.e. all counters 1 j,. .. 1 fr) is zeroed. At the end of the last

cycle element OR 4 exposes a zero potential at its output, and on the leading edge of the signal from the output of former 19, the trigger 5 is set to the zero state and blocks

further receipt of clock pulses through the element And 7. The sorting of numbers is over.

To sort the numbers with the device, starting with the maximum number, it is sufficient to write the numbers into the input counters 1 ;, t the reverse code and get the result from the zero outputs of the output counter 2.

Table continuation

21

FIG. / ppppppp

fpi / s.2 t

Claims (1)

A NUMBER SORTING DEVICE containing input counters, an output counter, a group of OR elements, a group of pulse shapers, a group of output elements AND, a group of inhibitory elements AND, an OR element, an input element And, the first input of which is connected to the clock input of the device, and the output connected to the summing input of the output counter and the first inputs of the inhibitory elements AND groups, the outputs of which are connected to the subtracting inputs of the corresponding input counters, the outputs of which are bitwise connected to the inputs respectively of existing OR elements of the group, the outputs of which are connected to the inputs of the corresponding pulse shapers of the group, the second inputs of the corresponding inhibiting elements of the AND group, and with the corresponding inputs of the OR element., the outputs of the output counter are bitwise connected to the information inputs of the output elements and groups, the outputs of which are the information outputs of the device, characterized in that, in order to increase the reliability when sorting equal numbers, the first and second triggers, register, and converter isla units in binary code, equal number counter, first and second elements OR-HE, first and second elements AND, reset pulse shaper, delay element, the outputs of the pulse shapers of the group connected to the corresponding bit inputs of the register, the outputs of the bits of which are connected to the inputs of the first element OR-HE and with the corresponding inputs of the converter of the number of units in binary code, the outputs of which are connected to the corresponding information inputs of the counter of equal numbers, the outputs of which are connected to the inputs of the second the OR-HE element, the output of which is connected through a reset pulse shaper with the synchronizing input of the first trigger and the inputs of the settings to the zero state of the register and the second trigger, the information input of which is connected to the logical input. units of the device, the inverse output of the second trigger is connected to the first input of the first AND element, the second input of which is connected to the output of the first OR-HE element and through the delay element to the second input of the And input element, the third input of which is connected to the direct output of the first a trigger, the information input of which is connected to the output of the OR element, the input of clock pulses of the device is connected to the third input of the first element And and the first input of the second element And, the second input of which is connected to the direct output of the second trigger, and SU „„ 1179317 the output is the output of the output permission and is connected to the control inputs of the output elements of the AND group and subtracting inputs of the counter of equal numbers, the input of the recording permission of which is connected to the output of the first AND element and the synchronizing input of the second trigger.