SU1304026A1 - Interruption device - Google Patents

Abstract

The invention relates to computing and can be applied while monitoring the correct functioning of a processor. The purpose of the invention is the interruption reliability of the interrupt device. The device allows you to stop the processor if after the arrival of the interrupt request signal, the processor does not react to it, and also to establish the source of the interrupt request. The interrupt device contains the register 2, the mask register 5, the element OR 6, the interrupt register 7, the pulse former 12, the trigger 13, the HE element 14, three groups 4, 16 and 18 And elements, the display unit 17, three decoders 19, 20 and 21 3 il. S cl (j} f / if

Description

The invention relates to computing and can be applied while monitoring the correct functioning of a processor.

The purpose of the invention is to increase reliability.

Fig. 1 is a schematic of the interrupt apparatus; FIG. 2 is a time diagram of the operation of the device during normal operation of the processor; FIG. 3 shows a time diagram of the operation of the device in the event that the processor does not respond to the interrupt request signal.

The device contains a processor 1, register 2, the first element IZ, the first group of elements AND 4, the register 5 of the mask, the element OR 6, the register 7 of the interruption of the scientific research institute, the control unit 8, the memory block 9, the pulse generator 10, the subscriber 11, the pulse former 12 , trigger 13, element NOT 14, second element 15, third group of elements 16, indication block T7, second group of elements 18, third 19, first 20, second 21 decoders and interface 22 and 23,

As a control unit 8 controlling the operation of the processor 1, known devices can be used; as a generator 12, a Schmidt trigger,

: The device works as follows.

The interruption of the operation of processor 1 can be carried out by any control signal received on the interrupt register 7. In this case, the input from 28 receives a signal from the control unit 8, the input to 27 receives a signal when performing a device self-test, the input 26 receives signals from subscribers 11 interacting with the processor 1, When interrupt signals appear on one or several inputs 26-28 register 7 interrupts at its output, in the corresponding bits, a signal equivalent to 1 appears. If interruptions on the corresponding bits are resolved by removing the mask from register 5, then through the corresponding AND element of the AND 4 group of elements and the OR element 6 comes with drove the input of a processor 1 24 and shaper 12. The shaper 12 is ensured formation of a definite duration signal, and after a certain time interval, i.e. control interval of time.

In the operation of the device, two modes are possible: I mode - processor 1 is normal; Mode II - no reaction of processor 1 to the interrupt request signal,

I mode The timing diagram of the operation of the device is shown in FIG. 2, having received the interrupt request signal.

to input 24, processor 1 goes to the interrupt processing program. The interrupt processing program provides for writing through interface 22 using a decoder 19 and group 18 elements, to the processor 1 register a reset signal code, which provides output 3 on element 3 a signal equivalent to 1. The occurrence of this signal ensures the cessation of the formation of a control time interval. Processor 1 continues to work on the program.

II mode The time diagram of the operation of the device 1 is shown in FIG. 3. Having received the interrupt signal, the processor

1 does not respond or reacts incorrectly, t, e, does not proceed to the execution of the interrupt program. In this case, after the formation of the control time interval has been completed, the trigger 13 is set to one and when there is no signal at the output 29 of the element 3 from the output of the element 15, a signal arrives at input 25 to stop the processor 1. The processor 1 terminates the execution of the program. the signal from the output of the element 15 goes to the elements 16 and resolves the indication of the state of the interrupt register 7, indicating to the operator the reason for stopping the processor 1.

Claims (1)

Invention Formula An interrupt device comprising first, second, and third decoders, a mask register, an interrupt register; The first group of elements is AND, the element is OR, and the informational inputs of the first, second and TpfeTbero are decrypted. The ditch is connected to the input of the device to connect the processor address to the bus; the outputs of the first and second decoders are connected to the read inputs of the mask register and the interrupt register, respectively; the write inputs of the mask register and the interrupt register are connected to the input of the device to connect to the write output of the processor; is a group of device interrupt request inputs, the inverse outputs of the bits of the mask register are connected to the first inputs of the AND elements of the first group, the outputs are Dov-register interrupt is connected to the second inputs of elements AND of the first group, the outputs of elements AND of the first group are connected to the inputs of the element OR, The second group is connected to the group of information inputs of the register, the outputs of which bits are connected to the inputs of the first element AND the output of which is connected to the K input of a trigger and through the element Ht to the first input of the second element AND, the output of the element OR pulses and is the output e with the fact that, in order to increase-fO devices for connecting to the input right now No reliability, the device contains a register, the second and third groups of elements And, the first and second elements And, the pulse shaper, the trigger, the element NOT and the display unit, with the 15 output of the third decoder connected to the first inputs of the elements And the second group, the second inputs of the elements And the second the groups are connected to the input of the device for connecting to the write output 20 of the processor, the third inputs of the elements of the second group are connected to the device input bits for connecting to the processor data bus, the outputs of the interprocessor interrogation, output The pulse generator is connected to the J input of the trigger, the output of which is connected to the second input of the second element I, the output of which is connected to the first inputs of the AND elements of the third group and is the output of devices for connecting the processor to the ic6poca, the outputs of the bits of the interrupt register are connected the second inputs of the elements of the third group, the output of the elements of the third group are connected with the group of inputs of the indication block. {Signal || stuffed Z7wu2B At 2 i At 29 k6. The second group is connected to the group of information inputs of the register, the bit outputs of which are connected to the inputs of the first element AND whose output is connected to the K input of the trigger and through the element Ht to the first input of the second element AND, the output of the element OR is connected to the input pulse generator and is the output interrupt request, the output of the pulse generator is connected to the trigger J input, the output of which is connected to the second input of the second I element, the output of which is connected to the first inputs of the AND third group and is the output of the device for connecting to the ic6poca input of the processor, the outputs of bits the interrupt register is connected to the second inputs of elements AND of the third group, the outputs of elements AND of the third group are connected to the group of inputs of the display unit. - / F1 / G.2 Signal on 26 silt and 7t // rt / 28 Hazff At 25 tK about fig.Z