SU807304A1 - Device for apparatus-programme testing and restoring sync pulses of digital computer - Google Patents

Description

This invention relates to computation (Telnaya Technique and can be used to detect failures in the interface channels of special devices with digital computers (UBM) to preserve the functionality of the system as a whole. A device is known for test monitoring I / O channels of a digital computer containing an interface , address registers, command registers, command decryptor, control unit, state byte generation unit, data generation unit, data register, and OR element l. (However, this device does not use to test in systems where it is not possible to perform operational processing of information at the rate of its arrival.The closest to the proposed technical entity is a device for controlling input / output channels of a digital computer containing a register that receives a test-program command code regimes, the implementation of the decoding of the command code, the block of imitation of recipes, processing the specific mode and the formation of a communication signal with the digital computer, the matching unit, organizing requests for information exchange with the digital computer 2. N The main thing with this device is that it does not take into account the violation and disappearance of the control sync signals and, in the absence of a sync signal, the Tepii T device functions as a whole. The purpose of the invention is to increase the reliability of the control. This goal is achieved in that the device for hardware and software monitoring and recovery of digital computer clock, block of information control, block for fixing failures, block of forming a communication signal with digital computer, and the output of block of information control is connected to the first input of block of fixing failures, block is entered receiving sync pulses, a signal level generator, a pusan block, an alarm condition word storage unit, an interrupt block, a sync pulse shaping unit, and a master oscillator, the output of the master oscillator It is connected to the first input of the sync pulse shaping unit, the first input of the information control unit and the first input of the sync pulse reception unit, the second input of which is the device sync pulse input and the output of the sync pulse generation unit whose output is connected to the second 1 INPUT of the information control unit , the first output of the block of fixation of failures is connected to the first entrance of the block of interruptions and to the second entrance of the block of formation of clock pulses, the output of which is the output of the clock device pulses, the second output of the block fixing failures connected to the third input of the block receiving clock pulses and. with the first input of the communication signal forming unit with a digital computer, the output of which is connected to the first input of the emergency state word storage unit, the second input of the latching failure unit, the second input of the interrupt unit and the first input of the start / stop unit, the second the input of the alarm state word storage unit and the second input of the communication signal shaping unit with a digital computer are the input of the device state word input the output of the alarm state word storage unit is the output of the device alarm state / second word d start-stop unit is an input device sharing start mode, the output start-stop unit is coupled to a fourth input of the receiving clock, an interrupt output block is output interrupt device.

The drawing schematically shows the proposed device.

The device contains a sync pulse reception unit 1, which is an assembly of two elements AND, a signal level generator 2 representing an RC chain, an information control unit 3 performed on the AND element, a fault fixation unit 4 performed on a trigger with a counting input, block 5 forming a communication signal with a digital computer, the start-stop unit, performed on the RS trigger, the emergency word storage unit 7, represents a diode array, the interrupt unit 8 and the sync pulse shaping unit, each performed on the AND element, giving generator 10.

The device works as follows.

In the initial state of the device, the resolving potentials from the output of the device start-stop block b are taken to the inputs of the synchro-pulse receiving unit 1 and from the output of the fault-fixing unit 4 for back-oscillator generator 10 and the digital clock sync pulses. The signals from the output of block 1 are fed to the input of the former -2 signal level, the output of which maintains a zero potential in the presence of a logical unit at its input and an exponential voltage increase occurs in the absence of these signals. The output of block 4 and the output of block 5 are prohibited in the initial state and in the absence of a large signal from the digital computer through blocks 8, 9 and 7.

Operation of the device begins when the signal from the digital computer starts the exchange mode to the input of block b, from whose output to the input of block 1 a zero signal is received, prohibiting the signal from the generator 10 from passing through block 1 of synchronization pulses to the signal level generator 2. In the event of a malfunction that led to a breakdown of exchange synchronization in the system and the absence of synchronous pulses of a digital computer at the input of block 1, the input signal of block 2 will have a zero signal, as a result of which the voltage at the output of block 2 begins to increase. After a time adjusted in block 2, the voltage reaches the response level of information control block 3, the output of which sends a signal to the counting input of the fault fixing unit 4 and changes the state of its outputs to inverse. One of the outputs of the block 4 of failures allows the issuance of a compensating synchronization from the master oscillator 10 through the clock generation unit 9 in the digital computer, and also enables the output of the interrupt signal to the digital computer through the interrupt unit 8. Another output of block 4 prohibits the operation of block 1 in order to avoid repeated triggers. The signal of the end of the exchange mode is fed through block 8 to the digital computer as an interrupt signal. In addition, it sets in the block 4 trigger, from the output of which a single signal is fed to the input of block 1 and to the input of the installation in block 1, with the result that the output of block 5 generates a signal for issuing a status word to the input of block 7 storing words of the state of the accident.

The use of the device allows to obtain a positive technical effect, since the device included in the information processing system makes it possible to compensate for the disappearance of clock pulses that are necessary for the digital computer to work in the request-response mode, while the digital computer does not enter the dynamic stop mode and can continue dey from subscribers.

In the digital computer, an interrupt signal is triggered by the interrupt signal coming through the device block 8, the readout of the state word is generated by which the state word code is read from the block 7 in the digital computer

Claims (1)

Claim A device for hardware-software control and recovery of clock pulses by digital computers, comprising an information control unit, a fault fixing unit, a signal generating unit for communication with digital computers, the output of the information control unit being connected to the first input of the failure fixing unit, characterized in that, in order to increase the reliability of control, a block for receiving clock pulses is introduced into it, - 20 a signal level former, a start-stop block, an emergency status word storage unit, a block interrupts, the clock generation unit and the master oscillator, the output 25 of the master oscillator being connected to the first input of the clock generation unit, to the first input of the information control unit and to the first input of the clock receiving unit, the second input of which is the device clock input, the output of the receiving unit clock pulses are connected to the input of the signal level driver, the output of which is connected to the second input of the information control unit, the first output of the fault fixing unit is connected to the first input of the unit and interrupts with the second input of the clock generation unit, the output of which is the output of the device clock, the second output of the fault fixing unit is connected to the third input of the clock reception unit and to the first input of the signal generation unit of the digital computers, the output of which is connected to the first input of the storage unit the words of the accident status, the second input of the fault fixing unit, the second input of the interrupt unit and the first input of the start-stop unit are the input end of the device exchange mode, the second the input of the emergency status word storage unit and the second input of the communication signal generating unit with digital computers are the reading of the device status word, the output of the emergency status word storage unit is the output of the device accident status word, the second input of the start-stop unit is the beginning of the device exchange mode input, the output of the start-stop block is connected to the fourth input of the clock receiving block, the output of the interrupt block is the interrupt output of the device.