SU1338059A1 - Pulse counter - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of counters with an arbitrary counting module. The purpose of the invention, an increase in the counting module, is achieved by introducing the pulse counter of switch 6, element NE-NE 7 and one-shot 8 into the pulse counter. The device also contains N bits, each i-th of which contains the T flip-flop li and D- trigger 2.1, input bus 3, forward outputs 4.1 T-flip-flops and 5.1 D-flip-flops of all bits. The delay in setting the code on the output bus does not exceed the response time of one D-flip-flop and does not depend on the number of digits of the counter. The operation of the counter is explained in the time diagram given by the fe description of the invention. 2 Il. (L CO SO oo ate with phi & 1

Description

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The invention relates to automation and computing and can be used in the construction of rosters with an arbitrary module of the network.

The purpose of the invention is to increase the mo account.

FIG. 1 shows a functional block diagram of an impulse counter; figure 2 - timing charts of his work.

The pulse counter contains N bits, each i-th of which contains a T-flip-flop 1.1 and a D-flip-flop 2.1, and the T-flip-flop 1.1 of the first bit and the clock inputs of the D-flip-flops of all N bits are connected to the input bus 3 The output of the T-flip-flop of each i-ro bit is connected to the D-input of the D-flip-flop 2.1 of the given bit. The direct outputs 4.1 of the T-flip-flops 1.1 and 5.1 of the D-flip-flops 2.1 of all bits are connected to the corresponding bits of the output bus. The direct outputs of the D-flip-flop 2.N and T-flip-flop 1.N N-ro bits are connected to the first and second inputs of the switch 6, respectively, the output of which is connected to the first input of the AND-NE element 7, the output of which through the one-shot 8 is connected to the installation inputs of all triggers, and the second input - with the installation bus 9.

The device works in the following way,

In the initial state, the counter triggers reset to zero. On the front of the first clock pulse (Fig. 2a), the T-trigger 1.1 triggers, which is reset to the logical zero state on the front of the second clock pulse (Fig. 26), in the D-trigger 2.1 on the front of the second clock pulse occurs write logical unit

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(Fig. 2c). The next clock pulse is 45 NAND elements, the first input of which

These trigger the D- and T-flip-flops of the next bits, as shown in FIG. 2, where the timing diagrams are presented for the case

Cutoff pulse (Fig. 2g) at the output 5 in the position of the switch 6, shown in Fig. I, the element AND NOT 7 forms the front of the pulse that triggers the one-shot 8, which forms

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a short pulse (Fig. 2h), resetting triggers of all bits of the counter. When the next cycle (for N 3 of the 12th) counting pulse arrives at pin 3, the counting cycle is resumed.

In the other position of the switch 6 (Fig. 2e), the counting cycle is completed when the 10th pulse arrives (at).

With a broken feedback circuit containing switch 6, element IS-HE 7 and one-shot B, the counter counting module is 2 (B dL). Introducing feedback allows you to increase the counting module to 11 or 10 with a particular position of the switch 6,

The delay in installing the code on the output bus of the counter does not exceed the response time of one D-Tpni-repa and does not depend on the number of counter bits.

Claims (1)

Invention Formula A pulse counter containing N bits, each of which contains T- and D-flip-flops, the T-flip-flop of the first bit and the clock inputs of the D-flip-flops of all bits are connected to the input bus, the T-flip-flop of each of the bits It is connected to the D-input of a D-flip-flop of this bit, the direct outputs of the T- and D-flip-flops of all digits are connected to the corresponding bits of the output bus, characterized in that, in order to increase the counting module, a switch, element NAND and one-shot, the output of which is connected to the installation inputs all x triggers, input - with output 0 connected to the installation bus, and the second with the output of the switch, the first input of which is connected to the direct output of the N-ro D-flip-flop, and the second - to the direct output of the N-ro T-flip-flop, and the inverse output of the D-flip-flop of each of the bits is connected to the input T-flip-flop for the corresponding most significant bit.