SU733111A1 - Counter on ring register - Google Patents

Description

The invention relates to electronic computing and automation devices that can be used to build meter circuits on ring registers with pre-installation and to build pulse distributor circuits. The counter on the ring register is known, which contains a ring register, each bit of which is built on three AND-NOT elements, eight additional AND-NOT elements, and I. In this device, six AND additional AND-NOT elements are executed according to the scheme of three triggers Tt trigger, the remaining two additional elements serve to invert the signals of the loan and transfer the It trigger 1. In the described device, three AND-NOT elements are consumed for each counter, and for organizing two series of clock pulses shifted relative to each other with eight elements and NOT. A counter on the ring register is also known, each bit of which consists of a trigger on two IS-NOT elements, containing two clock buses, a reset bus and four additional IS-NOT elements. The direct output of each bit of the ring register is connected to the first inputs of the installation in O and the previous one in the ring of discharge, the inverse output is connected to the second input of the installation in 1 next in the ring of discharge, the output of the first additional element AND-NOT connected to the first input of the second the output of which is connected to the first inputs of the first and third additional AND elements - NOT, the output of the last of which is connected to the first input of the fourth, the output of which is connected to the second inputs of the first and third additional AND elements , the second input of the fourth, the third input of the first and the third input of the fourth, the fourth input of the first complementary elements AND-NOT are connected respectively to the first and second clock buses, the installation bus to the initial state is connected to the fourth and fifth inputs of the fourth and fifth additional elements AND -NO, with the third installation input in the first O

3

ring bit .register, the third input of the installation of the first discharge of which and the second input of the installation of all subsequent odd bits to the O are connected to the output of the first additional AND NOT element,

with the second input of the installation in O of the last bit of the ring register, the third input of the installation of O of the last discharge of which and the second inputs of the installation of O of all previous even-numbered bits are connected to the output of the fourth additional AND-NOT element and with the third input of the installation of 1 second bit Yes, the third installation inputs in 1 of all subsequent bits, except the last, are connected to the direct input of the first bit of the ring register, the direct outputs of which even-numbered bits are connected to the inputs of the second additional element AND-NOT corresponding 2

The disadvantage of this device is

a large number of inputs of the second additional NAND element, which is one more than half of the number of bits of the ring register.

The purpose of the invention is to reduce .. the number

the inputs of the second additional element AND - N device simplification.

The goal is achieved by the fact that in the counter on the ring register, each bit of which consists of a trigger on the nejoc elements AND-NOT containing two clock busses, the resetting control panel and four additional elements AND-NOT, and the direct output of each bit ring register is connected to the first inputs Set in O and 1 of the previous. In the ring bit, the inverse output of which is connected to the second input set to 1 next in the ring bit, the output of the first additional element AND NOT connected to the first input second, the output of which is connected to the first inputs of the first and third additional NAND elements, the output of the last of which is connected to the first input of the fourth, the output of which is connected to the second inputs of the first and third additional AND elements, the second input of the fourth, third input of the first and the third input of the fourth, the fourth input of the first additional elements AND-NOT are connected respectively to the first and second clock of the installation bus to the initial state is connected to the fourth input of the fourth additional electric ment AND-NO element and to third input of setting to 1 the second annular discharge register, the outputs of the first and fourth additional AND-NO elements are connected to second inputs of the installation in G sootvetstvenpo even and odd bits annular re14

the inverse output of the first bit of which is connected to the third inputs of the device in O of the subsequent odd bits, the setting of the reset state is connected to the third input of the installation in the first 1 bit of the ring register and the second input of the second additional element AND NES, the third and the fourth inputs of which are connected to the direct outputs of the first and third bits of the ring register, respectively.

FIG. 1 shows a counter on a ring register with a conversion factor of ten; FIG. 2 a, b shows time diagrams of the device operation.

FIG. 1 is indicated; Ij-Ijo - the first elements of the IS-NOT of the triggers of the bits of the ring register, 2i-2io - the second elements of the triggers of the bits of the ring of the register, 3 -b additional elements of the IS-NOT, 7 - the first clock bus, 8 - the setting of the initial state , 9 - second tact bus.

In the ring register, in each bit, the direct output is connected to the first inputs of the installation in O and 1 of the previous discharge in the ring. So, for example, the output of the element AND-NOT li is connected to the first inputs of the elements AND-NOT 2j | j, lio, the output of the element b is connected to the first inputs of the elements AND-NOT 2 ,, li, etc. The inverse output of each bit of the ring register is connected to the second input of the unit to the next one in the ring bit. So, for example, the output of the element AND-NOT 2) 0 is connected to the second input of the element AND-NOT li, the output of the element AND-NOT 2i is connected to the second input of the element AND-NOT l, etc., the output of the element AND-NOT 3 is connected with the second inputs of the elements AND-NOT 2, 2.2, 2e, -2to and with the first input of the element AND-NOT 5, the output of the KOToiporo is connected to the first inputs of the elements AND-NO 3, 6. The output of the latter is connected to the first input of the element AND- HE 4, the output of which is connected to the second inputs of the AND-HE 2, 2z, 2s, 2t, 2, and 6, 3 elements. The reset bus is connected to the second input of the AND-HE element 4, to the third inputs of the AND elements -N E li, Ij and with the second input of the element AND-HE 5, the third and fourth inputs of which are connected respectively with the outputs of the elements AND-HE li, 1h. The output of the element AND-NOT 2j is connected to the third inputs of the elements 2z, 25, 27, 29, the bus clock pulses 7, 9 are connected to the third and fourth inputs of the elements AND-NOT 3, 4, respectively.

Claims (2)

The timing diagram of FIG. 2 a, b is shown taking into account the use of the NAND elements for positive signals at the input and taking into account the delays on the operation of the elements. The high potentials at the outputs of the elements of the device, which are caused by the low potentials coming from elements 3, 4, are plotted on the time diagram. The counter on the ring register works as follows. At the initial moment of time, the circuit in FIG. 1 was in a state (see FIG. With high potentials at the outputs of elements 4, 3, li, 22, b, 2h, 24, is, 2s, 2b, 1 ,, 2 ,, 2g, ig, 29, 2io, 6 to low potentials at the outputs of the elements 2i, 14, U, Is, lio 5 and on the bus 7. Since the potentials of the inputs of element 2 at the moment TO have high potentials, then at the output of this element at the moment equal to the time to act a low potential appears at the moment of TI. At the moment of Tz, an positive potential appears at the input 7, which causes through a time equal to the delay time for the operation of one element at the moment of the Tz of occurrence low potential at the output of element 4, since high potentials act at its inputs from the moment Tj. Low potential from element 4 enters the inputs of elements 6, 2j, 2h, 2s, 27, 2d and causes the appearance at time T4 at the output of element 2i high potential, which, in turn, causes a low potential at the output of element 11 at the moment of TS. Low potential from element b enters the inputs of element 5 and lio and causes a high potential at their outputs at the moment t high potential at the output of lio element causes a low potential at the moment on you ode element Ig, which in turn causes the time Tg at the outlet IB element a high potential. The high potential from element b arrives at the input of element IT, at the output of which at time T9 a low potential appears which, at the input of element Ig, reaches a high potential at the output of ti. At the time Tj i, the latter causes a low potential at the elemett Is output, which in turn causes a high potential at the output element U at the TU moment. High potentials at the outputs of the circuit elements, which are caused by low potentials coming from elements 3 and 4, are blackened in the time diagram. At the time of Ti2, a low potential appears at the input 7, which enters the input of the element 4. At its output at the time Tja, a high potential appears. The appearance of a high potential at the output of element 4 leads to the appearance of elements 2h and 6 at the outputs at the time TI 4 of a low potential. At the moment of TJ S, the falling edge of the negative pulse arrives at input 7, i.e. a positive potevdial appears. At the input of element 3 from this moment there are high potentials, and therefore from the moment of TI its low potential acts at the output. The latter arrives at the input of element-22, and at its output a moment in Tj, a high potential appears, which causes a low potential at the output of element b, which, in turn, causes the sequential operation of the elements Ij / .lio, b, le. I 1b, Is-At time T2 5 at input 7, a low potential appears, which results in a high potential at the output of element 3, which, in turn, causes a low potential at the outputs of elements 24 and 5. A low potential at the output of element 5 causes high potential at the output of element 6. At the time T28, the trailing edge of the third negative impulse arrives at input 7, which causes the sequential operation of elements 4, 2з, 1z, b li, lio, b) Is, IT, 1b, and the losses that occur at the output of each of the following elements from This p is the inverse potential Dial at the output of the previous item. At time T41, the falling edge of the fourth negative pulse arrives at input 7, which triggers the sequential operation of elements 3, 24, 14, b, b, Ii, bo, b, 18, 17. at the time of TS I, the front edge of the first negative pulse, element 3 is triggered, and at the output of the zero arm of the sixth trigger, i.e. at the output of element 2b, a low potential (negative pulse) appears. When the sixth negative pulse arrives at input 7, moment Tb 4, a negative pulse appears at the zero output of the seventh trigger (output of element 2,). At the arrival of the seventh, ninth negative impulses at input 7, a negative impulse appears sequentially at the cool outputs of the eighth, ninth and tenth triggers of the register. After the tenth pulse arrives at input 7, a negative pulse appears at the zero output of the first trigger, i.e. at the output of element 2i, and with the arrival of the following negative pulses at the input 7 of the counter, the counter operation nickname is repeated. With the arrival of each successive impulse to the input 7, the output us of the next triisr of the first statistics of the cheater appears. 7. The outputs of the counter are the outputs of the zero arms of the register triggers, and the code O of the counter corresponds to the value of zero at the zero output of the first register trigger, code 1 - low potential, at the zero output of the second peeter, cola 2 low potential and zero; trigger Similarly, the codes correspond to a low potential at zero outputs, respectively, 4-10-io register triggers. Information from the counter outputs is removed after the arrival of the falling edge of the negative pulse at the counter input. Tire 8 is a bus for installation of a counter E of a primary driver; 1 zero state. The installation is performed by a negative pulse. The formula is izvevetvenn The counter on the ring register, each discharge of which consists of a trigger on two elements AND-NOT, containing Two clock bus, the installation bus to its original state and four additional elements AND-NOT, and the direct output of each bit of the ring register is connected With the first inputs of the installation in O and 1 previous in the ring of discharge, the inverse output of which is connected to the second input of the installation in 1 subsequent in the ring of discharge, the output of the first additional element AND-NOT connected to the first input of the second th AND-NO element whose output is connected to the first inputs of the first and third a surcharge GOVERNMENTAL AND-NOT output of the last of which is connected to the first input chetvertog. 8 additional elements AND-NOT, the output of which is connected to the second inputs of the first and third additional elements AND-NOT, the second input of the fourth, the third input of the first and the third input of the fourth, the fourth input of the first additional elements of the AND-NO are connected respectively to the first and in the mountain clock In the process of installation, the initial setup is connected to the fourth input of the fourth additional AND-NOT element and to the third installation input to the 1 second bit of the ring register, characterized in that, in order to simplify the circuit, the outputs The first and fourth additional elements of the IS are NOT connected to the second inputs of the installation in O, respectively, the even and odd bits of the ring register, the inverse output of the first discharge of which is connected to the third inputs of the installation in O of the subsequent odd bits, the setting of the initial state is connected to the third input of the unit in the first 1 bit of the ring register and with the second input of the second additional IS-NOT element, the third and fourth inputs of which are connected to the direct outputs of the first and third digits of the number Dedicated register, respectively. Sources of information taken into account in the examination 1.Bukreev I.N. and others. Microelectronic circuits of digital devices, M., Sov. radio, 1975, p. 291, fig. 6.24. 2. USSR author's certificate in accordance with the application N "2561623/21, cl. H 03 K 23/02, 30.12.77 (prototype).