SU1218455A1 - Pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in information technology. The purpose of the invention is to expand the functionality achieved by adjusting the length of the output mpl. The device contains D-triggers f and 4, bus 2 clock pulses, inverters 3 and 12, logical element (LE) EXCLUSIVE OR 5, buses: control 6, output 7, 8 and 16, information 15, register 9, counter 10, Comparison unit 11, LE OR-NOT 13 and 14. In order to achieve this goal, the device additionally entered: register 9, counter 10, comparison unit 11, inverter 12, LE 13 and 14. 1 il. J5, g 00 ate cl

Description

The invention relates to a pulse technique and can be used in information and computing technology.

The purpose of the invention is the expansion of functional capabilities by adjusting the duration of the output pulses.

The drawing shows an electrical schematic diagram of the device

The pulse shaper contains the first) -thrigger 1, the C input of which is connected to the bus of 2. tact pulses and through the first inverter the 3rd C input of the second D trigger 4 ,. the output of which is connected to the first input element 5 EXCLUSIVE OR, the second input of which is connected to the output of the first D-trigger 1, whose D-INPUT is connected to the input control bus 6, as well as the first and second output buses 7 and 8, register 9, counter 10, a comparison unit 11, a second inverter 12, first and second elements 13 and 14 OR NOT, the first input of the second element 14 i. OR is NOT connected to the first input of the first element 13 OR is NOT to the input of the second inverter 12, to the counting resolution input of the counter 10, to the output of the comparison unit 11, the first group of inputs of which is connected to the registers 1 input 9, and the second group of inputs to the counter outputs 10, the input of installation zero of which is connected to the output

element EXCLUSIVE OR, the clock input of the counter 10 is connected to the bus 2 clock pulses, the information inputs of the register 9 are connected to the input information buses 15, the clock input of the register 9 is connected to the input control terminal 6, the output of the second inverter 12 is connected to the first output Bus 7, the output of the first element 13 OR is NOT connected to the second output bus 8, the second input of the first element 13 OR is NOT connected to the D input of the second 1 trigger 4 and the output of the first D flip-flop 1, the inverse output of which is connected to the second input of the second element 14 IL - NOT, the output of which is connected to the third output bus 16.

The pulse shaper operates as follows.

In the initial state upon arrival of the clock pulses on the bus 2

2184552

clock pulses and the presence on bus 6 of level O both T) triggers are set to the zero state, counter 10 in the state corresponding to the number written in register 9, at the output of unit 11 comparison is level 1, it is prohibited. counter 10, and at the output tires 7, 8 and 16 - level O.

 O When the input signal passes on bus 6 from state O to state 1, information stored on input data bus 15 is written to register 9. First

The 15 next to this event, the front of the clock pulse on the bus 2 clock pulses translates the D-trigger 1 to state 1, with the output of element 5 EXCLUSIVE OR output 20 level 1, which sets the counter 10 to state O At the output of the comparator unit 11, a level O appears, which enables the operation of the counter 10 and the driver

25 leads to the transition of the signal on the output buses 7 and 16 to the state 1. a cut of the clock pulse following this state on the bus 2 clock pulses converts the D-flip-flop 4 to

30 state 1, whereby at the output of element 5, the EXCLUSIVE OR appears level O, which is transmitted. to the input of the installation of zero counter 10 and allows it to work. Each following clock pulse on the bus 2 clock pulses increases the state of the counter 10 by one. This will occur until the state of the counter 10 is compared with the number recorded in the register 9. At the output of the comparison unit 11, a level 1 appears, which prohibits the operation of the counter 10 and translates the signals on the output buses

45 7 and 16 in state O.

When the input signal on bus 6 goes from state 1 to state O, the first clock edge following this event

A 5Q pulse on bus 2 places the ..D-flip-flop 1 into the O state, with

This is at the output of element 5, TYPE 1). OR 1 level appears, which sets the counter 10

JJ is in state O. At the output of the comparator unit 11, a level O appears, which enables the operation of counter 10 and causes the signal on the output buses 7 and 8 to go to state 1. The following cut-off clock pulse on bus 2 sets the D-trigger 4 to the state O, and at the output of element 5, the SCRIPTING OR the level O appears, which is transmitted

Impulses from 1 to 2 periods

ten

20

25

and the input of the installation of zero counter 10 and allows it to work. Each next clock pulse on bus 2 increases the state of counter 10 by one. This will occur until the state of the counter 10 is comparable to the number recorded in the register 9. At the output of the comparison unit 11, a level 1 appears, which prohibits the operation of the counter 10 and translates the signals on the output buses f and B to state O, the pulse builder returns to its original state.

Thus, the pulse shaper produces pulses synchronized by the front of clock pulses, the duration of the output of the limits

clock

pulses, where N is the size of the counter 10, register 9 and comparison block 11. On the output bus 7, pulses are formed on the front and edge of the control signal on bus 6, on the output bus 16 — only on the front on the output bus 8 — only on the slice. The pulse duration is determined by the information recorded from the input information bus 15 to the register 9.

The pulse shaper can be performed on microcircuits manufactured in series - (for example, series 564-564 ИР9, 564 ИЕ 10, etc.).

The proposed pulse shaper allows you to adjust the duration of the generated pulses, which expands its use. In addition, the generated pulses are synchronized with the front of clock pulses, which is necessary to control a combination of Composer B

Editor M. Dshin Tehred O. Nece

15

thirty

35

.45

Order 1138/60. Circulation 818 Subscription

VNISH1I USSR State Committee for Inventions and Discoveries 4/5, Moscow, F -35, Raushsk nab. 113035

Branch PPP Patent, Uzhgorod, st. Project, 4

1218A554

non-overlapping pulse sequences.

5 Formulas

the invention

A pulse shaper containing the first I) -trigger, the C input of which is connected to the clock bus and, through the first inverter, to the C input of the second D trigger, the output of which is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the output of the first -trigger, D-input of which is connected to the input control width, as well as the first and second output buses, characterized in that, in order to extend the functionality by adjusting the duration of the output pulses, a register, counter, block is entered into it comparison, the second inverter, the first and second elements OR NOT, the first input of the second element SH-NOT connected to the first input of the first element SH-NOT to the input of the second inverter, to the counter enable input of the counter, to the output of the comparison unit, the first group of inputs of which are connected with exits

register, and the second group of inputs

with the counter outputs, the input of the zero setting of which is connected to the output of the EXCLUSIVE OR element, the clock input of the counter is connected to the bus of clock pulses, the information inputs of the register are connected to the input information buses, the register input is connected to the input control bus, the output of the second the inverter is connected to the first output bus, the output of the first element OR-IE is connected to the second output bus, the second input of the first element OR-IE is connected to the D input of the second D trigger and the output of the first D Trigger, inverse output which is connected to the second input of the second element OR NOT, the output of which is connected to the third output bus. Chizhikov

Proofreader M. Przho,

Claims (1)

Claim A pulse shaper containing the first 5-trigger, the C-input of which is connected to the clock bus and through the first inverter to the C-input of the second D-trigger, whose output is connected to the first input of the EXCLUSIVE OR circuit, the second input of which is connected to the output of the first D-flip-flop, the D-input of which is connected to the input control bus, as well as the first and second output buses, characterized in that, in order to expand the functionality by adjusting the duration of the output pulses, a register, counter, block are introduced into it comparison, the second inverter, the first and second OR-HE elements, the first input of the second OR-HE element is connected to the first input of the first OR-NOT element, with the input of the second inverter, with the counter resolution enable input, with the output of the comparison unit, the first group of inputs of which connected to the outputs of the register, and the second group of inputs with outputs of the counter, the zero-setting input of which is connected to the output of the EXCLUSIVE OR element, the clock input of the counter is connected to the clock bus, the information inputs of the register are connected to the input information bus in other words, the register input is connected to the input control bus, the output of the second inverter is connected to the first output bus, the output of the first OR-NOT element is connected to the second output bus, the second input of the first OR-HE element is connected to the D-input of the second D -trigger and with the output of the first D -Trigger, whose inverse output is connected to the second input of the second OR-HE element, the output of which is connected to the third output bus. '• Chizhikov Proofreader M. Pozho. Order 1138/60 Circulation 818 Subscription VNIIIPI of the USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushskaya nab., D. 4/5 Branch of PPP Patent, Uzhhorod, st. Project, 4