SU1282314A1 - Pulse generator - Google Patents

Abstract

The invention can be used in the design of generators for synchronizing digital circuits. The purpose of the invention is the enhancement of functionality - achieved by changing the generated sync sequences and increasing the speed. To do this, the third 4 and fourth 5 registers are entered into the generator, the second memory block 7, the AND block 8, and the pulse counter 1. The generator also contains registers 2 and 3, memory block 6, the first 9 and second 11 control buses, synchronization bus 10, output buses 12. The generator can generate several types of synchronization 1X sequences. This is important when synchronizing a computer, since during operation of a computer, depending on the function being performed, the synchronization sequences must also change. 1 il. i (L

Description

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The invention relates to a pulse technique and can be used in the design of generators for synchronizing digital circuits.

The purpose of the invention is to expand the functionality by changing the generated sync series and increasing the speed of the pulse generator,

The drawing shows a functional block diagram of a pulse generator.

The pulse generator contains a pulse counter 1, registers 2-5, memory blocks 6 and 7, a block of elements 8, first control pins 9, a sync bus 10, second control buses 11, output buses 12, the sync bus connected to the sync rods the counter 1 and. registers 2 - 5. The control buses 9 are connected to the information inputs of the counter 1, the loan output of which is connected to its recording input. The information outputs of counter 1 are connected to ai

formation inputs of registers 2 and 3 The outputs of register 2 are connected to the lower address inputs of block 6, the outputs of which are connected to the information inputs of register 4. The outputs of register 3 are connected to the lower address inputs of block 7, the outputs of which are connected to information inputs of register 5. The outputs of registers 4 and 5 are connected to the inputs of the block of elements AND 8. The outputs of the block 8 are connected to the output bus 12, the control buses 11 are connected to the higher address inputs of blocks 6 and 7.

The pulse generator works as follows.

On the rising front of each clock pulse coming from the bus 10 clock signal, counter 1 changes its state by -1, registers 2 and 4 on the rising front of each clock clock bus 10 fix the previous state of the counter and memory block 6, respectively. Registers 3 and 5 on the falling front of each clock pulse from bus 10 record the current state of counter 1 and memory block 7, respectively. At the address recorded in register 2, the next word is read out from memory block 6, which is recorded on the rising edge of the sync pulse in register 4, and register 2 is entered

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The current state of the counter 1. At the address recorded in register 3, the next word is read from memory block 7, which is fixed by the falling

5 to the front of the clock in register 5, and to register 3 the new state of the counter 1 is entered. At the same time, the counter 1 changes its state by -1 on the rising front of the clock. So

 About occurs until zero is set in meter 1. In this case, the next sync pulse at the first output of counter 1 causes an impulse to appear on the rising 5th front of which the code from control bus 9 is written to counter 1. And the whole cycle is repeated again.

In each case, the code on bus 9 is hard-soldered. Regions 20 and 4 and 5 are necessary so that at the time of changing the address, the transient from the outputs of blocks 6 and 7 of the memory does not penetrate to the output buses 12 through the block of elements And 8 and does not cause a false trigger of the circuit. Registers 4 and 5 are recorded already installed with information from memory blocks 6 and 7, respectively.

Registers 3 and 5 and memory block 7 allow, at one input of a block of elements And 8, to obtain codes shifted relative to codes at other inputs of a block of elements And 8 by a half period of synchronous frequency. In the block of elements And 8

35, the summing of the like signals is carried out, as a result, at the outputs of block I 8, synchronicities are obtained whose period is a multiple of half the period of the synchronization frequency.

40 In addition, registers 2 and 3 play the role of conveyor registers and reduce the total cycle time of the generator, since they allow parallel operation of the counter 1 and blocks 6 and 7.

This provides an increase in the maximum frequency of the generated sync.

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The code on the control bus 11 determines the number of the addressable memory area of blocks 6 and 7, and hence the law of generation of sync series. When changing the code on bus 11, the addressable memory area and the law of generation of sync serials change. Thus, the same generator can generate several types of synchronization sequences without

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rework last. This is, however, when synchronizing a computer, when operating in the head of an executable function, synchronization functions are provided.

Claims (1)

Invention Formula A pulse generator containing a first register, the outputs of which are connected to the address address inputs of the first memory block, the outputs of which are connected to the information inputs of the second register, the synchronization input of which is connected to the synchronization input of the first register and the sync signal bus, characterized in that speed increase, the third and fourth registers are entered into it, the second memory block, the block of AND elements and the counter O 5 0 pulses, in which the loan input is connected to the recording input, and the subtraction input is connected to the clock signal bus and tpeTbero synchronous inputs and the fourth register, the third register outputs are connected to the lower address inputs of the second memory block, the upper address inputs of which are connected to the higher address inputs of the first memory these and the first control buses, and the outputs are connected to the information inputs of the fourth register, the outputs of which are connected to the first inputs of the block of elements And, the second inputs of which are connected to the outputs of the second register., and the outputs are connected to the output buses, while the information inputs of the first register are connected to the information inputs of the first register and to the information outputs of the pulse counter, whose information inputs are connected to the second control buses.