SU1233269A1 - Device for generating single pulses - Google Patents

Description

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The invention relates to information pulse engineering and can be used in automation systems and computer technology for generating single pulses on two channels. The purpose of the invention is to expand the functionality by generating several single pulses.

Figure 1 shows the functional diagram of the device; FIG. 2 shows the principal principle of a pulse key with soldering / injection of a control signal; on fig.Z - timing charts, which indicated: and the signal on the input bus 6; 5 - clock pulses on the bus 5; In the signal on the inverse output of the trigger 11; g - the first single impulse on the output bus 8; - signal at the direct output of flip-flop 2; e is the signal at the output of the element AND-NOT 4; W - the second single pulse on the output bus 9,

The device contains the first and second triggers and 2, inverter 3, element, 4, bus 5 pulses of the clock frequency, bus 6 of the control signal, pulse key 7 with memory

control signal, output pshny 8 and 9 If you need to get the third single pulse of the H, the device contains. additionally the third trigger 10, the element AND-NOT 11, the inverter 2, the element And 3, the third input bus 14,

The device is working (next in the same way.

In the initial state, the triggers 1 and 2 are in the state O, on the output buses 8, 9 and 14 the signal O is set, the clock pulse from the bus 5 through the key 7 is fed to the second input of the element AND NOT 4, but does not pass on its output, as at the first input of the element AND-NOT 4, the signal O, coming from the output of trigger 2

The impulse from the bus 6 arrives at the counting input of the trigger 1 and switches it to state 1, while the O signal is set at the control input V of the key 7. The first clock pulse from the bus 5, which came after the control signal from the bus 6, goes to the input switch C of the key 7, switches to its first output and switches the triggers 1 and 2, and the trigger 1 switches to

the state is O, and the trigger 2 is in the state. The next clock pulse is computed at the second output of the pulse key 7 and is fed to the second input of the NAND 4 element, the first input of which has a signal 1 from the output of the trigger 2, while a pause between the signals is generated at the output of the NAND 4 element (Fig. ), which is converted by the inverter 3, and the trigger 2 is switched by the falling edge of the pause pulse to the initial state.

Thus, the formation of two pulses on tires 8.9, synchronized and my clock frequency. When the forg-shrovanip on the output bus 14 of the third single pulse, the trigger, 10, elements 1i and 12, work similarly to the trigger 2, elements 4, 3, while the output of the element 13 and the pulse is formed 1-1 after switching the trigger 2 into O state

five

0

0

The device uses a pulse key 7 with a backup of the control signal (1), which contains the switching input 15 C, the control input 16 Y, logic elements 17-20, the inverter 21J outputs 22 and 23, logic elements 17-20 can be performed on the elements RSHI-NOT when switching signals 1 (system RTL, DTL; MjQJI-Transistors) or at the elements AND-NOT when switching signals O (system TTL),

Key 7 when switching signal 1 operates as follows. In the initial state at input 15 and at outputs 22 and 23. there are signals O, at the control input we set the signal O, Signal 1 at input 15 causes appearance of signal O at the output: inverter 21, while at all inputs of the OR element -NO 19 signals O are set, and at its output a signal.

The change of the control signal at input i 6 during the commutation of signal 1 1e affects the commutation due to the presence of feedback from outputs 22 and 23 to the inputs of the elements PI-HE 20 and 19, respectively, and there is also the presence of feedback from the outputs 22 and 23 to the inputs of the elements OR NOT 7 and 18, respectively.

Thus, the pulse duration at the input I5 of the switching and on

five

50

55

the outputs 22 and 23 of the switch 7 are always the same; the duration of the pulses is not affected by the change of the control signal at the control input 16 during the switching of these pulses from the switching input I5 to one of the outputs,

Claims (2)

1. A device for generating single pulses, comprising first and second triggers, an inverter, a clock frequency pulse bus, a control signal bus, characterized in that, in order to expand the field of application, an IS-NOT element and a key with a control signal are entered into it, the control input of which is connected to the inverse output of the first trigger, connected to its D-input, the counting input of the first trigger is connected to the control signal bus, and the R-input reset to the first output bus, S-input of the second trigger setup and ne vym output pulse wrench latched control signal, which is input by switching dklyuchen to the bus clock pulses, a direct output of the second five ten five 0 five 0 the trigger is connected to the first input of the NAND element, the output of which is connected to the input of the inverter and with the counting input of the second trigger, the D input of which is connected to its inverse output, the second input of the NAND element is connected to the second output of the pulse key with the storage of the control signal, and the inverter output is connected to the second output bus. 2. The device according to p. I, about tl and -. often, in order to expand the field of application, a third trigger, an AND element, a second AND-NOT element and a second inverter, the output of which is connected to the third output bus, and the input to the output of the second AND-NOT element and with counting input. the third trigger, the D input of which is connected to its inverse output and the installation S input to the inverter output, while the direct output of the trigger is connected to the first input of the third NAND element, the second input of which is connected to the output of the AND element, the first and The second outputs of which are connected respectively to the inverse output of the second trigger and to the second output of the pulse key with a memory of the control signal. J5 o 2 Fmg.Z