SU1559397A1 - Controllable shaper ofd pulses - Google Patents

Abstract

The invention can be used in devices of automation and computing. The purpose of the invention is to expand the functionality due to the additional simultaneous formation of a burst of pulses and controlled by the duration of the output pulse - the use of the fourth 10 and fifth 11 match elements, the third 3 and fourth 4 triggers, the second output bus 16 is achieved. The device also has triggers 1 and 2, inverters 5 and 6, coincidence elements 7-9, pulse counter 12, control bus 13, bus 14 clock pulses and output bus 15. 2 Il.

Description

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The invention relates to a pulse technique and can be used in automation and computing devices.

Belle of the invention - enhanced functionality due to the additional simultaneous formation of a burst of pulses and controlled by the duration of the output pulse

The following is an electrical functional circuit diagram of the device; Fig. 2 are time diagrams for his work,

The controlled pulse shaper contains the first, second, third, and fourth triggers 1–4, the first and second inverters 5 and 6, the first, second, third, fourth, and fifth elements 7–11, the counter 12 and their pulses.

The S input of the first trigger 1 is connected to the control bus 13, the direct output of which is connected to the first input of the first coincidence element 7, the second input of which is connected through the first inverter 5 to the bus 14 of clock pulses, to the first input of the second coincidence element 8 and Medium with a counting input of pulse counter 12, the reset input of which through the second inverter 6 is connected to the inverse output of the second trigger 2, the R input of which is connected to the third input of the first matching element 7 and to the output of the third matching element 9,

The outputs of the pulse counter 12 are connected to the corresponding inputs of the fourth and fifth elements 10 and 11 of coincidence, the additional inputs of which are connected respectively to the direct and inverse outputs of the third trigger 3, whose C input is connected to the output of the third coincidence element 9, R input with the first output of the first flip-flop 1 and with the first R-input of the fourth flip-flop 4, the second R-input of which is connected to the first input of the third element 9 coinciding with the R-input of the first trigger 1 and the output of the fourth element 10 - with the release of and the second input of the third element 11 and the matcher 9, the forward output - with an input of the second WTO ring element 8 coincidence, the output of which is connected to the first output line 15 and the second

the output bus 16 is connected to the direct output of the fourth trigger 4,

The shaper works as follows,

In the initial state on bus 13 there is no control signal (unit level). Bus 14 (FIG. 2a) has an input continuous pulse sequence that is inverted by element 5 (FIG. 26). At the direct output of flip-flop 1, the zero level blocks the coincidence element 7, as a result of which a single level is set at the output. Trigger 2 is in the zero state and the single level of the inverse output is inverted by element 6 to the zero level, by which the counter 12 is held in the initial zero state and does not allow the output pulses of element 5 to produce an account. The zero level of the direct output of the trigger 1 keeps the trigger 3 in the zero state. In this case, the unit level of the inverse output of the trigger 3 unlocks the element 11, and the zero level of the direct output blocks the element 10,

At the outputs of elements 10 and 11, there are unit levels that pass to the output of element 9 by a unit level. Trigger 4 — in the zero state. The zero level of its direct output keeps the bus 16, element 8 and the bus 15 in the zero state. When the control signal arrives at the bus 13 (FIG. 2c), trigger 1 is set to one (FIG. 2d) and allows inverted output output pulses of element 5 (FIG. 26) to pass through element 7 with zero signals (FIG. 2d).

The first zero output signal of the coincidence element 7 sets the trigger 2 to the one state via the S input. In this case, a zero level appears at its inverse output (Fig. 2e). This level is inverted by element 6 (fig. 2g) by one. A unit output level of element 6 allows summing counter 12 to recalculate. Summing counter 12 produces on the falling edge of each pulse of the bus 14, summing to its unit content (FIG. 2h). The recalculation occurs until the sixth state (110) is established in the summing counter 12. The sixth state of counter 12 is decrypted by element 11 (Fig. 2i). At the zero level of the output signal of the element 11, the trigger 4 is set to one. At the same time, on bus 16, a pulse delayed by six steps of an input continuous sequence is formed and at the same time unit 8 is unblocked by a single level of direct output of trigger 4, Zero output signal of element 11 passes through element 9 (FIG. 2l), blocks element 7 (FIG. 2d) and sets trigger 2 to zero. In this case, the unit level of the inverse output of the trigger 2 (Fig. 2e passes through the element 6 by the zero level (Fig. 2g) and sets the counter 12 to the initial zero (000) state. On the zero state of the counter 12, the elements 11 and 9 return to the initial state, element 7 is unblocked, the setup signal is removed from the R-input of the trigger 2, and the trigger 3 is set to the single state (FIG, 2n, o) at the counting input. The zero level of the inverse output of the trigger 3 blocks the element 11, and the single direct output level allows operation of the element nta 10, At the output of element 7, the zero level of the signal appears again (fig 2d), according to which the trigger 2 is set to one and the signal of setting to O is removed from the R input of the counter 12, the counter 12 performs the summation of pulses arriving at the counting input (Fig. 2h). Element 8 transmits bus 14 pulses to bus 15 (Fig. 2i). At the end of the fourth bus pulse 14, a fourth state (100) is set in the counter, which is decrypted by element 10 (Fig. 2m) . By the zero output signal of the element 10, the trigger 4 returns to the initial state. In this case, a pulse with a duration equal to four cycles of the input continuous pulse sequence is formed on the bus 16. The zero level of the output signal of the element 10 coincidence when removing the control signal from the bus 13 makes the initial installation of the trigger 1, the initial wiring of the trigger 2 and the counter 12 is performed similarly to working off

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signal of the zero level of the element 11 output. By the zero level of the direct output of the trigger I, the trigger 3 returns to the initial state. After

bringing the device to sleep mode. The next control signal to the bus 13 repeats the process of forming and extracting pulses,

If the zero output signal of the element 10 is received at the R-input of the trigger 1, and at this time the control signal is present at the S-input, then the trigger 1 saves the unit level at the forward output. The device after the initial installation of the counter 12 and the trigger 3 works similarly signals on the bus 16 and

Q pulses on bus 15 until the control signal is removed from bus 14.

The proposed driver, depending on the connection of the inputs

5 points 10 and 11 to the outputs of the counter 12 allows forming delayed up to K cycles on the bus 16 (where K is the counter conversion factor; the cycle is equal to the period between pulses of the Q sequence of pulses) pulses of duration from one to K cycles and selecting on the bus 15 from one to k pulses.

The number of generated pulses on the bus 16 is determined by the duration of the control signal bus 13,

Claims (1)

Invention Formula 0 five A controlled pulse generator containing the first trigger, the S input of which is connected to the control bus, the direct output to the first input of the first match element, the second input of which is connected via the first inverter to the clock bus, to the first input of the second coincidence element and directly with the counting input of the pulse counter, the reset input of which is connected via the second inverter with the inverse output of the second trigger, the R input of which is connected to the third input of the first matching element and to the output of the third element a matcher, a first output line, which is connected with the output of the second coincidence element, characterized in that, in order to expand functionality five for additional simultaneous formation of a burst of pulses and controlled by the duration of the output pulse, the fourth and fifth coincidence elements, the third and fourth triggers, and the second output bus are introduced into it, and the outputs of the pulse counter are connected to the corresponding inputs of the fourth and fifth elements matches, the additional inputs of which are connected respectively to the direct and inverse outputs of the third trigger 1ТШППШШППППШи Pa, Ogohod which is connected to the output of the third element of the match, R-input - with the direct output of the first trigger and the first R-input of the fourth trigger, the second R-input of which is connected to the first input of the third element of the coincidence, with the R-input of the first the trigger and with the output of the fourth match element, the S input with the output of the fifth and with the second input of the third match element, the direct output with the second input of the second match element and with the second output bus.