SU1200389A1 - Device for selecting single pulse - Google Patents

Description

The invention relates to a pulse technique and can be used in various devices for converting, processing and transmitting information.

The aim of the invention is to increase the speed and reliability of the device.

Figure 1 shows the structural diagram of the proposed device; figure 2 - timing diagrams explaining the operation of the device.

A device for selecting a single pulse contains a bus 1 control signals, the bus. 2 clock pulses, the first 3 and the second 4 inverters, the first 5 and second 6 elements AND-NOT, the first 7, the second 8 and the third 9 EZ-triggers and the element 10.

Bus 1 control signals associated with the third inputs of the first 5 and second 6 elements AND-NOT and with the K-input of the second short-circuit trigger 8, the inverse output of which is connected to the second inputs of the first 5 and second 6 elements AND-NOT, the outputs of the first 5 and second 6 elements AND-NOT are connected respectively to the input of the third KZ-trigger 9 and 3-input of the first KZ-trigger 7, 3-input of the third KZtrigger 9 connected to the bus 2 clock pulses and the input of the first inverter 3, the output of which is connected to - the input of the first trigger 7, to the first input of the first element NAND 5 and, through the second Inverter 4, to the first input of the second element AND-NOT 6, the first input of the element 10 and 10 is connected to the direct output of the third trigger 9, the second input to the inverse output of the first trigger 7, and the output of the element 10, which is the output of the device, is connected to 8 the input of the second short-trigger 8.

The first 7, second 8 and third 9 short-circuits are triggers with inverse inputs, i.e. controlled by low (zero) logic levels. '

The device works as follows.

In the initial state on the bus 1 control signals there is a zero voltage level,

On bus 2 (fig.2b) clock pulses - clock pulses, at the outputs of the elements AND-NOT 5 and 6, short-circuit triggers

1200389 ²

7-9 and element And 10 - unit voltage level.

Upon receipt at the time ΐ _{ι (} bus 1 (figv) of the control signal of the unit voltage level at the output of the second element AND-NE 6 (fig.2d), a zero voltage level appears, which is fed to the 3 input of the first short-circuit trigger 7 (Fig. 2g). At the output of the first KZ-flip-flop 7, the unit voltage level does not change, since at its K-input there is also a zero voltage level from the output of the inverter 3 (Fig. 2a).

At time ^(P R ^{and the} appearance of a single voltage level at the output of the first inverter 3), the first RS flip-flop 7 is switched (as on its 8-input single voltage level appears later than in the K-input to the delay of the signal through a second inverter 4 and the first element 25 AND-NOT 6) and at its output appears zero voltage level, which is supplied through the element 10 (fig.2i) to the 3rd input of the second short-circuit trigger 8 (fig.2z) and to the output device ^wa ·

When a second short-voltage trigger 8 appears at the 3 input of a zero voltage level, it switches and a zero voltage level appears at its inverse output, which is applied. the inputs of the elements AND-NOT 5 and 6 (Figg, d) prohibits the passage through them of clock pulses.

At the moment of time b * (when a single voltage level appears at the output of the first inverter 3), a zero voltage level pulse appears at the output of the first NE-5 element, the duration of which is $ 4 equal to the switching time of the second short-circuit trigger 8. At the same time, the third short-circuit trigger 9 does not change its state, since at its 3-input there is a zero voltage level coming from the bus 2 clock pulses.

At time ί _? (when the output of the inverter 3 zero voltage level) the first short-trigger 7 switches and at its inverse output appears a single voltage level, which is supplied to the second input element And 10. By 10

15

20

3

How many at the first input element.

And 10 there is also a unit voltage level from the output of the third KB trigger 9 (Fig. 2e), then a unit voltage level also appears at its output (device output), i.e. the formation of the output pulse ends.

When at the time of time on the bus 1 control signal

zero voltage level, the output of the second KB-trigger 8 appears a single voltage level, i.e. The device returns to its original state.

When a single voltage level control signal appears on bus 1 at a time, the device also generates a single pulse at its output, with the only difference that now a zero voltage level appears at the output of the first AND-NOT element 5 (as in inverter 3 unit voltage level).

At the moment of time переключ _6, the third KB trigger 9 is switched and, from its output, a single pulse emitted, through

1200389

four

element I 10 enters the output of the device and the 8-input of the second EB-trigger 8. At the end (at time ₇ ) of the control signal on bus ₅ not 1 second short-trigger 8 is reset to the initial state (a single voltage level appears at its output ), and the formation of a single pulse output device

10 continues until the time of the Burden, when a zero voltage level appears on the bus 2 clock pulses, which returns the third short-circuit trigger 9 and the entire device

15 as a whole in the original 'state.

To ensure the operability of the device when a control signal arrives on its bus 1 that coincides in time with a single or

20 with a zero state of a continuous pulse sequence received on bus 2, the duration of the control signal must be at least T / 2 + & 6, where T is the period of follow-up of the pulses of a continuous pulse sequence, and & ΐ is the time required for triggering the CB trigger 9 (or 7).

*

P.-GP —1 {—1 1—11- * ABOUT - “Ί g ~ π πη one-, and ............ _t • 1 G ......... - 1 g I — g ............

Claims (1)

DEVICE OF THE DAY OF ALLOCATION OF A SINGLE PULSE, containing the first and second K5-triggers, the first and the second elements NAND, the first and second inverters, the control signal bus, the clock pulse bus connected through the first inverter to the first input of the first NAND element, 1? - the input of the second B5-flip-flop is connected to the control signal bus; the output of the second inverter is connected to the first input of the second AND-NOT element, different mother-in-law, that, in order to increase speed and reliability, the third K5 trigger and the I element are entered, the first input which is connected to the direct output of the third K5 trigger, the second input is connected to the inverse output of the first H5 trigger, and the output of the AND element is connected to the 5th input of the second K5 trigger, the second input of the first I-NOT element is connected to the inverse output of the second IZ-trigger and with the second input w the third element of the first element and the third element is connected to the third input of the second element and the NOT control signal bus, the output of the first element 1e is connected to the TH input of the third short circuit trigger, the 5th input of which is connected to the clock bus pulses, the output of the first inverter is connected to the K input of the first 83 flip-flop and the input of the second inverter, the output of the second element is NOT connected to the 9-input of the first 85 trigger. 50 thirty >