SU1133666A1 - Pulse sequence frequency divider - Google Patents

Abstract

A PULSE FREQUENCY DIVIDER containing a frequency dividing unit whose input is connected to the clock frequency bus, a gating unit whose input is connected to the control bus, and a logical element block consisting of the first and second And elements, whose outputs are connected to the output through the OR element bus device. 2 characterized in that, in order to increase the speed, the first and second inverters and two pairs of compliant MOS transistors are introduced into it, the first of which is included in the forward output circuit of the gating unit and the first input of the first element And logical element unit, and the second is in the inverse output circuit of the gating unit and the first input of the second element AND block of logic elements, the second inputs of the first AND of the second elements And of which are connected via the first and second inverters respectively to the direct and inverse outputs and dividing the frequency block and hence to the gate electrodes of MOS transistors of different conductivity opposite pairs of complementary MOS transistors. CO & e 9d 05 a

Description

"1) The invention relates to an imp; 1 technology and can be used in frequency synthesizers. The known pulse frequency sequence divider contains a clock generator, a binary counter, buffer and information registers, a trigger and logic elements AND, OR, AND-OR D The disadvantage of this device is the limited speed due to the large number of frequency control stages. The closest to the invention to the technical essence is a device comprising a frequency division unit, the input of which is connected to the bus clock frequency, a gating unit, the input of which is connected to the control bus, and a block of logic elements, the first inputs of the matching elements which are connected respectively to the direct and inverse outputs of the frequency division unit, and the second ones, respectively, with direct and inverse outputs of the gating unit, and outputs, via element 1BI, with the output bus of the device, the clock frequency bus is connected a gating unit inputs the clock block logic elements 2. This device is not fast enough due to the dependence of the performance of the elements at the maximum (clock) frequency. The purpose of the invention is to increase the speed. The goal is achieved by the fact that in the frequency divider of a pulse sequence containing a frequency dividing unit, the input of which is connected to the clock frequency bus, a gating unit whose input is connected to the control bus, and a block of logic elements consisting of the first and second elements AND , the outputs of which are through: the element OR are connected to the output bus of the device, the first and second inverters and two pairs of compliant MOS transistors are introduced, the first of which is connected to the direct output circuit of the gating unit and the first input the first element AND block of logic elements, and the second - in the inverse output circuit of the gating unit and the first input of the second element And the logical input unit, the second inputs of the first and second elements And through the first and second inverters are connected respectively to the direct and inverse outputs the frequency division unit and, accordingly, with the gates of MOS transistors of the opposite conductivity of different pairs of complementary 1UP transistors. The (jMr.l shows a structural electrical circuit of the frequency divider of the pulse sequence; and figure 2 shows timing diagrams, explaining the operation of the device. The frequency divider of the pulse sequence contains a frequency division block 1, the input of which is connected to a clock frequency bus 2, gating block 3 The input of which is connected to the control bus 4, and the block of logic elements 5, consisting of the first 6 and second 7 elements AND, whose outputs through the element OR 8 are connected to the output bus 9 of the device, the first 10 and second 11 inverters and two pairs 12 and 13 of complementary BSS transistors, the first of which 12 are included in the direct output circuit of the gating unit 3 and the first input of the first element 6 and the block 5 logic elements, and the second 13 in the inverse output circuit of the gating unit 3 and the first input of the second element 7 and a block of 5 logic elements, the second inputs of the first 6 and second 7 elements, and through which the first 10 and second II inverters are connected respectively to the direct and inverse outputs of the frequency division unit 1 and respectively to the gates of MOS transistors of the opposite pr conductivity different pairs 12 and 13 UP-complementary transistors. In the device, the function of block 1 is performed by a dynamic frequency divider by two5, the function of block 3 is performed by the paraphase sial former, and the functions of block 5 by the element 2 X 2 and 2OR-NOT. The device works as follows. On the outputs of block 3, at any moment of time there are dissimilar pulses (Fig.22, d). The bus 2 of the device receives pulses (Fig. 2a) of the input frequency, and at the outputs of block 1, antiphase pulses are formed (Fig. 28, b), the frequency

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KOTophtx is half the frequency on bus 2. As a result, the keys formed by pairs 12 and 13 alternately open and close. In this case, the logic levels from the outputs of block 3 arrive at the first inputs of elements 6 and 7 of block 5 (FIG. 2e), permitting one of the two antiphase pulse sequences from the outputs of block I to pass to bus 9.

Each time a change on the control signal bus 4 is changed to opposite logical levels at the first inputs of elements 6 and 7 of block 5. However, the specified logical levels change only at times when a logical zero level is present at the second inputs of elements 6 and 7. The delay of the switching control pulses at the switching time of the MOS transistors is compensated for by the delay in the inverters 10 and 11 (Figures 2 and k). In this case, the elements 6 and 7 of the block 5 carry out the switching of the pulses coming from the outputs of the inverters 10 and 11 without cutting in duration. As a result, at the output of block 5, at the moment of switching the pairs 12 and 13, there are no short false pulses (fit. LAu).

36664

Thus, the moments of a signal change on bus 4 result in the exclusion of one half-period from the output pulse sequence, which is equivalent to the exclusion of one whole period of the input frequency on bus 2; this corresponds to an increase per unit conversion factor of the device.

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Instead of complementary MOS transistors, separate MOS transistors can be used in the device, however, when operating at high frequency, means should be provided to compensate for interference from the gate circuit. Unit 5 can also be made with other logic elements with the necessary phase observance

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Compared with the prototype, this device has more speed (almost twice), since 25 switching is performed by two-input frequency pulses. With an integral device, the reduction of high-frequency circuits leads to a simplified topology of the most critical part of the crystal and an increase in the maximum operating frequency. JUULTUULfU LJLJLnJLJlJU

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Claims (1)

A PULSE FREQUENCY DIVISER, comprising a frequency division unit, the input of which is connected to the clock bus, a gating unit, the input of which is connected to the control bus, and a logic block consisting of the first and second AND elements, the outputs of which are connected via the OR element to the output bus devices, characterized in that, in order to improve performance, the first and second, inverters and two pairs of complementary MOS transistors are introduced into it, the first of which is included in the direct output circuit of the strobe block of the first input of the first AND element of the logical unit block, and the second in the inverse output circuit of the gating unit and the first input of the second AND element of the logical element block, the second inputs of the first and second second elements And through the first and second inverters are connected to direct and block inverse outputs in frequency divisions and, correspondingly, with gates of opposite conductivity MOS transistors of different pairs of complementary MOS transistors. ΦυιΤ SU 33666 1133666 1