SU813749A1 - Selector of pulses by duration - Google Patents

Description

(54) SELECTOR OF PULSES OF DURATION

The invention relates to a pulse technique and can be used in the development of a decoding scheme with the suppression of false pulses. A pulse selector is known in duration, containing a delay element, an NAND element, the first input of which is connected to the device input, and a input of the delay element, a second input on the output of the delay element, a trigger, the first input of which is connected to the output of the NAND element, the second input is with the output of the delay element 1. The disadvantage of this device is the passage of spurious short pulses to the device output. This happens in the case when short pulses arriving at the first input of the NAND element coincide with short pulses that have passed through the delay element and arrived at the second input of the NAND element. The closest in technical dryness to the present invention is a device containing three delay elements, a pulse shaper, two inverters, an And element and a trigger, the first input of which is connected to the input bus, the shaper input. the output of which is connected to the first input of the element I, and with the input of the first delay element, the output of which is connected through the first inverter to the second input of the trigger. the output of which is connected to the inputs of the second and third delay elements, the output of the second delay element being connected to the second input of the AND element, and the output of the third delay element through the second inverter to the third input of the AND 2 element. The disadvantage of this device is that it does not restores the duration of selectable pulses. The purpose of the invention is to eliminate spurious pulses at the output of the device while maintaining the equality of the durations of the input and output pulses. The goal is achieved by the fact that the selector impulses in duration, containing three delay elements, an inverter and a trigger, the first input of which through an inverter is connected to the output of the first delay element, whose input is connected to the input bus, a key is entered, whose input is connected to the input bus, and outputs - with taps of the first delay element and the element IS-NOT, the first input of which is 11dk; 1yuchen to the first input of the trigger, the second input of which through the third delay element is connected to the output of the element IS-NOT the second input of which through the second delay element is connected to the output of the first delay element.

FIG. 1 shows a structural electrical circuit of the device; in fig. 2 - time diagrams that show his work.

The device contains the first delay element 1 with taps, the key 2, the input of which is connected to the input of the delay element 1 and the input of the device, the taps of the delay element 1 connected to the key 2, the second delay element 3, the input of which is connected to the output of the delay element 1, an inverter 4, the input of which is connected to the output of delay element 1, elect. AND-NOT 5, one input of which is connected to the output of inverter 4 and the other to the output of delay element 3, the third delay element 6, the third input of which is connected to you. the course of the element AND-NOT 5, the trigger 7 is static , the first input of which is connected to the output of the inverter 4, and the second - to the output of the delay element 6. The output of the trigger 7 is the output of the device.

On fi1 2 marked

l --- the delay time of the element 1 zade | 1zhki;

 36-time delay of delay element 6;

Tr and the duration of the input pulse.

The device works as follows.

Pulses are applied to the input (Fig. 2a). G1) and the absence of a signal at the input, the key 2 is open and the taps of the delay element 1 are connected with a common thickness (see Fig. 1), i.e.: mounted. If the input pulses (Fig. 2 a) are shorter in duration than the time; Supporting tj of delay element 1, then at the output and the last one, these pulses are absent, since at the end of the input pulses the key 2 opens and the delay element 1 is shunted. If the duration of the input pulses tn is longer than the delay time -f., The delay element 1, then at its output we get pulses (Fig. 2 b) with a duration equal to - g. These pulses are received on the input side of the inverter 4, from which output (Fig. 2 g) are sent to the first input of the trigger 7, forming the leading edge of the output pulses (Fig. 2 g). The two-sided pulses (Fig. 2b) arrive at the input of the delay element 3, are delayed by an amount less (Fig. 2c) and arrive at one of the inputs of the AND-NO element 5, to the other input of which pulses arrive (Fig. 2 d) from the output of the inverter 4. At the output of the element AND-HE 5, pulses are generated (Fig. 2 d) tied to the trailing edge of the pulses (Fig. 2 d). The generated pulses (Fig. 2 d) are delayed by delay element 6 by the amount of sec. tii- The received pulses (Fig. 2 e) from the output of the delay element 6 are fed to the second input of the trigger 7, forming the rear edge of the output and pulses (Fig. 2 g). As a result, when pulses 7 arrive at the inputs of the trigger (Fig. 2g, e) lagging each other by an amount (see Fig. 2) C "-tj i, Ti, at the output of the trigger 7, which is the output of the device, pulses are formed (Fig. 2g), equal in duration to the input pulses (Fig. 2a), but shifted in time by the value of Kz1 5b. Using the invention allows to increase the reliability of pulse selection with a duration t, more than t eliminate the passage, pulses with a duration of Tm less than T-ji tj {,. At the same time, the durations of the input and input selectable pulses are equal.

Claims (2)

1. USSR author's certificate number 618845, cl. H 03 K 5/18, 1977. 2. USSR author's certificate number 229597, cl. H 03 K 5/20, 1967.1 figl