SU1330737A1 - Pulse edge and droop shaper - Google Patents

Abstract

The invention can be used in systems for processing pulse information as a synchronizing device. The purpose of the invention is 1 and - to eliminate the delay of the rear front of the output pulses relative to the leading edge of the clock pulses. The shaper contains a D-flip-flop 1 and 7, the element AND-NOT 4 the inverter 6 and the elements AND 11 and 12 V device The element OR 3, the elements 8 delays are given .; D-trigger 10 and new functional connections are formed. 2 silt (-0 00 co O | SAE

Description

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The invention relates to the pulse-1 technique and can be used in the processing systems of the pulse in-, and as a synchronizing device.

The purpose of the invention is to eliminate the delay of the falling edge of the output pulses relative to the leading edge of the clock pulses.

Figure 1 shows the electrical circuit diagram of the device j in Figure 2 - timing diagrams explaining its operation,

The front-end and decay pulse generator contains the first D-flip-flop 1, the O-input of which is connected to the information bus 2, the first input of the OR 3 element and the first input of the NAND 4 element, the R-input connected to the output of the Sh1I 3 element, S- the input is with the output of the NANDA element, the C input is with the bus of 5 clock pulses and the input of the inverter 6, and the output is with the D input of the second D flip-flop 7, the C input of which is connected to the output of the inverter 6 and the input of the element 8 delays, R-input - with igina 9 Reset and R-rokhoj third D-flip-flop 10, right my way - with p-input flip-flop 10, the first input of the first ele And 11, the second and the input element 1SHI 3 and the second input element I-iiE A, and the inverse of the 11th input - with the first input of the second element; | ENTI 12, the Ki iToporo is connected to the first you-: -: The second input is with the Bi.xo,;, oM D-flip-flop 10, C-KOToporci C-input with the output of the 8 delay valve element, and the L-port - with the second; .1 T1: And 11, output one otoo is connected with the second Bigh; one innoi 14.

The form1 pulse torner on the front and in the decay works as follows. In the initial state, the D-triggers 7 and 10 are in the zero position (FIG. 2, k, k). In the absence of a single pulse on bus 2, trigger 1 is also in the zero position (Figure 2d), since its S-input has a single signal and the R-input has a zero signal. At the outputs elemental And 11 and 12 there are no pulses (figure 2 l, m). If, when a zero signal appears on bus 9, a single signal appears on bus 2 (Fig. 2a), then trigger 1 is set to a single position on the leading edge of the trigger signal that was received after the clamp.

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a single signal to the bus 2 clock pulse from the bus 5 (figb). Since the triggers 7 and 10 are not set to a single position, no output pulses are output to the output buses 13 and 14, and after the termination of a single signal on the bus 2, the trigger 1 is set to the zero position.

To bring the former into operation, it is necessary to send a unit-level signal to bus 9.

When a single impulse appears on bus 2, trigger 1 is prepared

to transfer to a single position, since a single signal appears at its R input, the single signal at the S input remains unchanged. The front of the first after the appearance of a single

the signal on the bus 2 clock pulse from the bus 5 trigger 1 is set to one position. If during the monitoring time equal in this case t ,, t j + t ° + t ° (where t is for the duration of the clock pulse on ish- 5), the input pulse on bus 2 will change from one to zero, then This input pulse is considered to be interference and the trigger 1 at the time of the appearance on the bus 2 of the zero signal is set to zero position by the zero signal from the output of the element OR 3 (Fig. 2c). If during the monitoring time the impelles on the bus 2 remain at a single level, then on the leading edge of the pulse from the code of the HE 6 element (on the leading edge of the clock pulse pause), the trigger 7 is set.

in one position (Fig. 2e), delay element 8 is simultaneously launched (Fig. 2i). At the occurrence of a signal of a single level at the unit output of the trigger 7 is prepared

Trigger 10 is triggered because a single signal appears at its D input, the operation of element OR 3 at the second input is blocked and AND 11 is turned on, the output of which

A single signal appears on bus 14. After a time (G at the output of the delay element 8 a signal appears, on the leading edge of which the trigger 10 is set to a single position, a zero signal appears at the second input of the element. And a zero signal appears at its output and the output signal 14 ends at a single signal. Thus, an impulse is formed on the bus 14.

the corresponding, to the leading edge of the NMT puls arriving on bus 2, is a synchronous pause of clock pulses.

When a zero level noise appears in a pulse on bus 2 with a duration less than the monitoring time, a single signal appears at the output of the NAND element 4 and therefore trigger 1 on the C input is enabled. If the interference coincided in time with the leading edge of the clock pulse from the bus 5, then the trigger 1 is set to the zero position. At the moment of the end of the interference, i.e. When a single signal appears on bus 2, the AND-HE 4 element is triggered and the trigger 1 is set to the single position again.

After the termination of the signal on bus 1 on the leading edge of the first clock pulse after this from bus 5, trigger 1 is set to zero. If during the monitoring on bus 2, no unit level pulses are received, then on the leading edge of the pulse from the output of the NOT 6 element (the leading edge of the pause of the clock pulses) the trigger 7 is set to the zero position, while the delay element 8 is simultaneously started. In connection with the disappearance of a single signal, a single signal appears at the single output of the 7 Fia trigger, the output of the NAND 4 element and a zero signal at the output of the OR 3 element. When a single signal appears at the zero output of the trigger 7, element 12 triggers and a signal appears on the output bus 13. After a time on the leading edge of the pulse from the output of the delay element 8, the trigger 10 sets to the zero position, one pulse is generated and a pulse is generated, 1ЧН1Т - branching to the trailing edge of the pulse received on bus 2, synchronous pause of clock pulses. The pulse shaper at the front and in the decay returns to its original state.

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Claims (1)

Invention Formula ten A pulse shaper on the front and decay, containing an inverter, the input of which is connected to the overcoat of clock pulses and the C input of the first 1) -trig1ger D input which is connected to the control bus and the first input of the NAND element, S input with output element NAND, and the direct output - with the D-input of the second D-flip-flop, the direct output 20 of which is connected to the second input of the NAND element and the first input of the first element AND, and the inverse P1, the stroke to the first input of the second element AND, the output of which is connected to the first input 25 bus, the second output bus connected to the output of the first AND element, different so that, in order to eliminate the delay of the falling edge of the output pulses relative to the leading edge of the clock pulses, the Sros bus, the third D-trigger, the 1PI element and the delay element, whose input is connected to the inverter taps and the C-input, are entered into it  the second D-flip-flop, and the output is from the S-C input of the third FJ-flip-flop, the R-input of which is connected to the Reset bus and the R-input of the second D-flip-flop, the D-input to the direct output of the second D-flip-flop, 40 inverse output - with the second input of the first element And, and the direct output - with the second input of the second element And, while the R-input of the first D-flip-flop is connected to the output of the OR element, the main signal is at its single & ode, pbtfi input of which is connected to the control output of the I 12 element and at the output bus, and the second input is connected to the forward bus 13. Thus on the bus output of the second D-flip-flop. 37. one 13 a pulse is formed and issued, 1ЧН1Т- corresponding to the falling edge of the pulse arriving on bus 2, a synchronous pause of clock pulses. The pulse shaper at the front and in the decay returns to its original state. Invention Formula ten A pulse shaper on the front and decay, containing an inverter whose input is connected to the overcoat of clock pulses and the C input of the first 1) trigger, whose D input is connected to the control bus and the first input of the NAND element, S input with the output of the element NAND, and the forward output is with the D-input of the second D-trigger, the forward output which is connected to the second input of the element AND-NOT and the first input of the first element AND, and the inverse P1, the stroke to the first input of the second element AND whose output is connected to the first input bus, the second output bus connected to the output of the first AND element differing in that, in order to eliminate the delay of the falling edge of the output pulses relative to the leading edge of the clock pulses, the Sros bus, the third D-flip-flop, the 1PI element and the delay element, whose input is connected to the inverter taps and C-input, are entered into it the second D-flip-flop, and the output is from the S-C input of the third FJ-flip-flop, whose R-input is connected to the Reset bus and the R-input of the second D-flip-flop, the D-input to the direct output of the second D-flip-flop, the inverse output is with the second input of the first element I, and the direct output is with the second input of the second element I, while the R input of the first D-flip-flop With Ostliitei ;, S, Yermakov lexiifit M.HrdanichKorrektor A.Obruchar J.iK: i; i) Circulation 901 Subscription lilininni State Committee, USSR :; ne, 1: am inventions and discoveries I SOiS. ; -ic i; Kiia; k-35, Raushsk nab., d.4 / 5  i - - VV P 1 ;; ng; -П1: п; (gp; fichesky enterprise, Uzhgorod, Proektna str., 4