SU1256154A1 - I-k flip-flop with clocking - Google Patents

Abstract

The invention is intended for use in automation and telemechanic devices. The purpose of the invention is to improve the noise immunity of an activated trigger. The trigger contains elements OR-NOT 4-11, inputs 1-3, and outputs 14 and 15. The introduction of elements OR-NOT 12 and 13 contributes to the fact that interference signals that may occur at the inputs of the trigger can affect the operation of the circuit only during the first clock cycle, after switching the clock signal from zero to one, and not during two clock cycles. 1 il. W

Description

eleven

The invention relates to a pulse technique and is intended for use in automation and telemechanic devices.

The purpose of the invention is to increase the interference resistance of a clocked trigger. The drawing shows a diagram of a clocked 1K-trigger.

The trigger contains three inputs 1-3, elements OR-NOT 4-13, outputs 14 and the First input of the first element OR-NOT 10 is connected to the output of the second element OR-NOT 11 and to the first input of the third element OR-NOT 4, the first input of the second element OR NOT 11 is connected to the output of the first element OR NOT 10 and to the first input of the fourth element OR NOT 5, the first inputs of the fifth 7 and sixth 8 elements OR are NOT connected to the outputs of the seventh 6 and eighth 9 elements OR-NOT, the second inputs of the fifth and sixth eight elements OR are NOT combined and connected to the first input 2 clocked 1K latch, and their third inputs connected respectively to the output 8 of the sixth, the second input of the second 11, the first input 9 of the eighth OR-NO elements and the output of the fifth 7, the second input of the first 10, the first input 6 of the seventh NOR elements. The second inputs of the third 4 and fourth 5 elements OR-NOT are connected respectively to the second 1 and third 3 inputs of a clocked 1K flip-flop.

The first input of the ninth element OR NOT 12 is connected to the output of the first element OR NOT 10, the second input of the ninth element OR NOT 12 is connected to the second input of the eighth element OR NOT 9 and the output of the fourth element OR NOT 5, the output. the ninth element OR NOT 12 is connected to the second input of the seventh element 6 OR NOT, the first input of the ten element OR NOT 13 is connected to the third input of the seventh element OR NOT is the bis output of the third element OR NOT 4, the second input of the tenth element OR-NOT 13 is connected to the input of the second element OR-NOT 11, the output of the ten element OR-NOT 1 3 is connected to the third input of the eighth element OR NOT 9.

The device works as follows.

Denote the signal at the output of the i-ro element through Z ,, where i is the position number of the element in the drawing, then

tri-ram i-nri C scheme of my equations

Z

I v q q q

(ABOUT

 four

The elements OR-NOT 10 and 11 form a bistable cell, realizing; an asynchronous RS flip-flop with direct inputs. The inputs of the bistable cell are the signals Z, vi Z., From the system (1), by substituting, we determine the values of the signals Z and Zg JZ C-Zg (Q (KVO)) IZg C-Z, (ZgV KQ V Q (IVQ)). (2) Nrie () is obtained from system (2), (a bistable cell formed by the elements OR-NOT 10 and 11 retains its previous state).

When switching the clock signal C from O to 1 at the first moment of time (initial state),, ZZ 0. At the next moment after switching the clock signal C from O to 1 (first clock), as follows from the system (2 ), the signals Z and Z g take values

| Z l-6 (OvTQ VQ (KVQ)) iQ VKQ

  , - -

lZg I-CCOVKQ VQ (IVQ) KQ VIQ.

Depending on the values of the signals I, Cyrus, the next time after the clock signal is switched, the time point (first clock) signals Z HZ

 8 get the values:

at,

Z, T-Q V About Q 0 Zg b Q V 1-Q Q vQ 1, with

 Z 7 0-Q V 1 Q Q VQ 1

  I Q V 0- Q 0, with

fz, b Q vo- Q q

lZ3 0. Q vo Q Q, with I, K 1

rz, - QVI -Q Q

(Zg 1 Q V t. Q 0.

Thus, the next after switching the clock signal MO3

time point (first tact) values of signals Z, and Z are set in accordance with the values of input signals I, K of output signal O in the state of LS 1, 2.0, or Z 0, Z 1, as this is required by the 1K operation algorithm -trigger

Then, at the next moment of time (second cycle), the values of the signals Zj and Z will be determined as follows:

ABOUT

2

for the case of Z 1,

rz, D (IQ V KQ vl) 1

IZg b I (KQ VIOVO) 0, for the case of Z, O, Zg 1

fZ, 01 (V0) 0

Zg 66 (KQ V 10 V 1). Consequently, the values of the input signals I and K affect the values of the signals Zj HZ only at the first time after switching the clock signal from 1 to O, i.e. only in the first clock cycle after the switching of the clock signal C. Then the signals Z and Z are blocked by the feedback circuit and regardless of the value of the input signals I and K retain their new value. Interference signals that may occur at the trigger inputs may affect the operation of the circuit only during the first cycle of the circuit after switching the clock signal from zero to one, and not during two cycles, as is the case with the known trigger.

Claims (1)

Invention Formula A clocked 1K-trigger containing eight elements OR-NOT, three inputs and two outputs, the first input of the first element OR-NOT connected to the output of the second element ORED Editor V. Petrash Order 4834/55 Circulation 816 Subscription VNIIL of the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Rau-ska nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 1544 NOT and with the first input of the third element OR-NOT, the first input of the second element OR-NOT is connected to the output of the first element RTOi-HE and the first input of the fourth element OR-NOT, the first inputs of the fifth and sixth elements OR-NOT connected to the outputs, respectively the seventh and eighth elements OR-NOT, the second inputs of the fifth and sixth elements OR-NOT are combined and connected to the first input of a clocked 1K-flip-flop, and their third inputs are connected respectively to the output of the sixth, the second input of the second, first input of the eighth elements OR- NOT and exit n In addition, the second input of the first, the first input of the seventh OR-NOT element, the second inputs of the third and fourth OR-NOT elements are connected to the second and third inputs of a clocked 1K-trigger, respectively, in order to increase the resistance of the trigger, Two elements are entered into it. CHI-NOT, the first input of the ninth element OR-NOT connected to the output of the first element OR-NOT, the second input of the ninth element OR - did NOT connect if to the second input of the eighth element OR-- E and to the output of the fourth element ISH5-NOT , the output of the ninth element OR is NOT connected to the second input of the seventh element OR NOT, the first input of the ten element OR is NOT connected to the third input of the seventh element OR NOT and the output of the third element OR NOT, the second input of the tenth element OR -NOT connected to the output of the second element OR NOT, the output of the tenth element OR NOT with united with the third input of the eighth element OR NOT. Compiled by L. Simonova Tehred M. Khodanich Proofreader I. Muska