SU1599974A2 - Clocking device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is to increase the noise immunity by additional filtering of negative short-term interference - by introducing the fourth and fifth triggers 4 and 5, the inverter 7. 1 Il.

Description

The invention relates to a pulse technique, can be used in automation devices and computing devices, and is additional to the author. St. f 898601.

The purpose of the invention is to increase the interference by filtering negative short-term interference.

FIG. 1 shows the electrical functional scheme of the device; in fig. 2 - time diagrams that show his work.

The device contains the first, second, third, fourth, fifth triggers 1-5, element AND-NOT 6, inverter 7,

The D and R inputs of the first trigger 1 are connected to the control bus 8, the direct output is connected to the D input of the second trigger 2, the direct output of which is connected to the D input of the third trigger 3, the inverse output of which is connected to the first input of the I- element NOT 6, the second input of which is connected to the D and R inputs of the third trigger 3, the third input with the C inputs of the first, second, fourth and fifth triggers 1-5 and,

with the clock pulse bus 9, the output with the output bus 10, and the control bus 8 through the inverter 7 is connected to the D and R inputs of the fourth trigger, the third output of which is connected to the D input of the fifth trigger 5, the S input of which is connected with direct output-, with the course of the second trigger 2, direct output - with the S-input of the second trigger 2.

The clock synchronization device operates as follows.

In the initial state, the triggers 1–3 are in the state O, the triggers and 5 are in the state 1. With the arrival of the high level information signal, the trigger t is set to the state O, and the trigger 1 is allowed to write 1 to the D input. With the arrival of the clock pulse 1 is recorded in the trigger 1. If the duration of the input signal is sufficient to overwrite from the trigger 1 to the trigger 2, then a high level signal appears at its output, causing the output signal of the clock signal at the output and releasing the lock on the S input trigger

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5. With the arrival of the trailing edge of the clock signal, the trigger 3 is set to state 1, which eliminates the appearance of the clock pulse at the output of the device until trigger 2 returns to its initial state. If the duration of the input signal is not sufficient to overwrite 1 from trigger 1 to trigger 2, then trigger 2 will not trigger and the pulse on bus 10 of the device will not work, trigger 5 remains in state 1. Thus, the device suppresses all which is less than 1 / fT. If the signal duration is greater than 3 / fT and there is a negative short-term interference, the duration of which is less than I / ft, the following occurs: after rewriting 1 into trigger 2, the lock is released from trigger 5 on the S input. With the arrival of the clock edge, since de potential is present at D-BXO, a low potential is present in it, O is recorded and a low level signal from its output blocks the operation of trigger 2 at the S input (keeps it in a logical 1 state). Since the duration of the negative short-term interference is less than 1 / fT, it does not affect the state of the trigger 5 and the state of the output signal. After the end of the information signal on the front of the second clock

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the pulse from flip-flop Q to flip-flop 5 is rewritten 1 and the high level signal from flip-flop 5 unlocks the S-input from flip-flop 2. With the arrival of the front of the third clock pulse, the flip-flop 2 is set to the O state trigger 5. The circuit comes to its original state.

Claims (1)

The proposed device allows to increase the noise immunity due to the protective time interval, which blocks short-term positive interference and short-term negative interference whose duration is less than 1 / fT. Invention Formula Clock device on aut. St. If 898601, о.т л and h ay e with the fact that, in order to increase the noise immunity by additional filtering of negative short-term interference, an inverter, fourth and fifth triggers, C-inputs of which are connected The D-and R-inputs of the fourth trigger are connected to the control bus through the inverter to the control bus, the direct output is connected to the input of the fifth trigger, the S input of which is connected to the forward output of the second trigger, the S input of which is connected to the right My exit from the first trigger. p p p p p p HL P J A AND one FIG. 2