SU1203692A2 - Device for suppressing noise - Google Patents

Abstract

The invention relates to video technology and automation, can be used in pulse shapers with interference suppression, and is additional to auth. St. No. 519857. The purpose of the invention is to improve the noise immunity of the device. The device contains triggers 1 and 2, 5 and 6, device input 3, inverter 4, device control input 7 and device output 8. The introduction of inverter 4 and triggers 5 and 6 allows suppressing negative polarity interference (negative polarity interference - short-term loss of a single signal at the control input of the device) and, therefore, double the number of correctable errors. 2 Il. FIG. /

Description

The device relates to computing technology and automation, can be used in pulse shapers with interference suppression, and is an improvement of the invention according to the authors. St. No. 519857.

The aim of the invention is to increase the noise immunity of the device by suppressing the negative polarity interference (negative polarity interference - briefly passing a single signal to the device control input).

FIG. 1 shows a functional diagram of the device; in fig. . time diagrams.

Device for interference suppression contains two triggers 1 and 2, the separate-installation inputs of which are combined, trigger synchronization input 1 is device input 3, single output of trigger 2 is device output, single output of trigger 1 is connected to single input of trigger 2, single the input of which is combined with its synchronization input, the zero input is grounded, and the inverse output is connected to the single input of trigger 1, and the inputs of separate stats-ev in O of both triggers 1 and 2 are combined, the inverter 4, the third and fourth triggers 5 and 6, inv The output of the second flip-flop 2 is connected to the input of the separate installation in and fourth of the flip-flop 6, and the inputs of the separate installation at the O flip-flops 1 and 2 are connected to the output of the inverter 4, the input of which is connected to the input of the separate installation of the third flashing-off 5 input device 7, information input J of the third trigger 5 is connected to the inverse output of the fourth trigger 6, and the single output of the third trigger 5 is connected to information input J of the fourth trigger 6, information input K of which is connected to the common bus, and e inichny output is the output device 8, the clock inputs of flip-flops 5 and 6 are combined with the input of the first synchronization flip-flop 1.

FIG. 2 are designated: and - a signal on an input of 3 synchronization; b - signal at control input 7, to signal at trigger output 5, g - signal

at the output of the inverter 4; d is the signal at the output of the trigger 1, e is the signal at the inverse output of the trigger 2; W is the signal at the output B of the device.

The device works as follows.

In the initial state at the control input 7 of the device there is a zero signal, which is the trigger

5 is set to the zero state when the power supply voltage of the device is turned on and thereby prohibits the operation on input J of flip-flop 6. One-. temporarily at the inputs of the R-flip-flops 1 and

2, a single signal is present that allows triggers 1 and 2 to be set to an arbitrary state. But a maximum after a time equal to two periods of clock pulses after switching on the supply voltage at the inverse output of trigger 2 a zero signal appears, which sets trigger 6 to the zero state, which corresponds to the initial state of the device.

When a single signal is applied to the control input 7 of the device, the operation of the flip-flops 1 and 2 is prohibited and the operation of the flip-flops 5 and 6 is permitted.

The fall of the first incoming clock pulse received at the synchronization input of device 3, the trigger

5 is set to a single unit. If a single signal on

the control input 7 of insufficient duration, less than the period of the following clock pulses, then the flip-flop of the trigger 6 in the unit state by the decay of the next clock

no pulse occurs, and trigger 5 will return to the zero state. And if the duration of a single signal at control input 7 is longer than the period of the clock pulse, then when the trace of the resting clock pulse is triggered, the trigger 6 is set to one and a logical unit signal appears at the output 8 of the device. Zero signal with inverse trigger code

6 prohibits the trigger 5 from being set to one.

When a zero signal is applied, and. If negative signal is interrupted at the device control input 6, the first clock pulse that arrives after the zero signal is applied or after

3

the effect of negative-polarity interference on the control input b of device trigger 1 is set to one.

If the duration of the negative polarity interference at the control input of the device 7 is shorter than the period of the clock pulse, the recovery of a single signal at the control input 6 of the device sets trigger 1 to the zero state, and trigger 5 confirms its zero state without disturbing the signal output 8 of the device. And when a zero signal is applied or when negative polarity is interrupted at the device control input 7 for a time longer than the clock pulse following period, when the second clock pulse decays, trigger 1 becomes zero, and trigger 2 becomes one. The zero signal from the inverse output of the trigger 2 prohibits the installation of the trigger 1 in the unit state and sets the trigger 6 to the zero state, which corresponds to the zero signal at the output.

Thus, using a noise suppression device can double the number of

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0

15

3692

correctable errors compared with the known device.

Claims (1)

Invention Formula Interference suppressor St. No. 519857, characterized in that, in order to improve noise immunity, an inverter and the third and fourth triggers are introduced into it, the inverse output of the second trigger is connected to the input of a separate installation on the fourth trigger, and the inputs of the separate installation of the first and second trigger are connected to an output an inverter whose input is connected to the input of a separate installation in O of the third trigger and is the control input of the device, information input 3 of the third trigger is connected to the inverse output of the fourth trigger, and the single output retego trigger 5 is connected to the invariant formational input of the fourth flip-flop having an information input K is connected to the common bus, and a single output is the output device, wherein the clock inputs of the third and fourth flip-flops are combined with the first input of synchronization flip-flop. 20 0