SU1451835A1 - Pulse series shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used to form a series of pulses under the conditions of a pulse interference at the control input of the device. The aim of the invention is to improve the reliability and noise immunity of the device. To achieve this goal, trigger 2 is inserted into the device for forming a series of pulses. The device also contains a pulse counter 1, triggers 3,4, element 5, control bus 6, clock bus 7, synchronization bus 8, code buses 9, reset bus 10 and the output bus 11. 1 Il.

Description

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The invention relates to a pulse technique and can be used to form a series of pulses under the conditions of a pulsed disturbance at the control input of the device.

The aim of the invention is to improve the reliability and noise immunity of the device.

The drawing shows the functional electric circuit of the described

devices.

The device for forming a series of pulses contains a pulse counter 1, triggers 2 and 3, additional trigger 4, element 5, control bus 6, clock pulse bus 7, synchronization bus 8, code buses 9, reset bus 10 and output bus 11,

Code bus 9 is connected to the information inputs of the pulse counter 1. The recording input of the pulse counter 1 is connected to the output of the element AND 5. The reset bus 10 is connected to the S input of trigger 2. The D and R inputs of the trigger 2 are connected to the control bus 6. The C input of the trigger 2 is connected to the inverse output of the trigger 4, the direct output of which is connected to the counting input of the trigger 3 and to one of the input of the And 5 element, the second input of which is connected to the inverse output of the trigger 2 and the R input of the trigger 3 and S - by the input of the trigger 4, the D-input of which is connected to the transfer output of the pulse counter 1, the counting input of which is connected to the bus 7 clock pulses. Bus 8 synchronization is connected to the C-input of the trigger 4.

Device to form a cross

The pulse pattern works as follows.

When the device is initially turned on (the device is initially turned on), a reset pulse (low potential) is applied to the bus 10, which sets the device to its initial state.

In the initial state, the output of the trigger 2, the inverse output of the trigger 4 and the output of the element 5 and the output bus 11 of the device contain a low:; potential, and a high potential on the control bus 6 of the device and the direct output of the trigger 4. The bus 7 of the device receives a stable sequence of clock pulses with a frequency F ,. On tire B

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synchronization is received by synchronizing pulses with frequency P ,. Pulse counter 1 is in recording mode, so that the code combination present on the device’s code 9 buses is recorded in

counter 1.

When a low level signal arrives on bus 6, trigger 2 switches and a high potential is established at its inverse output. Since, at the same time, at both the inputs of the element And 5 there is a high potential, the high potential established at its output puts the counter 1 and pulses into the subtraction mode. The clock pulses that arrive on bus 7 are then subtracted from the number N written in counter 1 in the binary code. When the pulse N-ro arrives at counter 1, the low potential at counter transfer output 1 arrives at trigger input 4. Upon arrival of a synchronizing pulse to bus 8, trigger 4 switches and a high potential is established at its known output, and a low potential is reached on the forward path, which through element 5 takes the input of the pulse counter 1, which goes t into write mode. Binary code combination from bus 9 is written to counter 1.

If by that time the signal on control bus 6 has already finished, which indicates that bus 6 had an interference pulse, not a useful signal, then when a high potential appears on the inverse output of trigger 4, the trigger 2 is switched to its initial state In this case, the trigger 4 is switched to the initial state, triggering of the trigger 3 and the occurrence of a signal on the output bus 11 are prevented. The device is brought to the initial state. Thus, in this device, the control signal is monitored for duration, i.e. The device does not respond to a pulse at its output, which acts on the control bus 6. The duration of the interference pulses suppressed by this device is determined by the code on the tires 9 and the clock pulse period.

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If at the moment of high potential occurrence, the inverse output of trigger 4 on bus 6 still has a low potential (this g indicates that bus 6 has a control pulse, not an interference pulse), then switching of trigger 2 does not occur, those. saves the previous state. When the next sync pulse arrives on bus 8, trigger 4 is switched. At the inverse output of trigger 4, a low potential is set, and at a forward high potential, from which trigger 3 occurs, and an output pulse begins to form on the output bus. At the same time, the high potential of the direct output of the trigger 4 passes to the output of the element And 5, puts the counter 1 into the subtraction mode and begins to subtract the incoming clock pulses from the previously recorded binary code of the number N. At the end of the N-ro pulse at the transfer output of the counter 1 along is the low potential that arrives at the D input of the trigger 4. When the clock pulse arrives on the bus 8, the trigger 4 switches and its high potential is set to its inverse output, and a low potential is set to the forward one, NT And 5 is fed to the input of the record of the counter 1 and translates it into the recording mode. If by that time the control pulse on bus 6 has already finished, then when a high potential appears on the inverse output of trigger 4, trigger 2 is switched to its initial state. The low potential from the inverse output of the trigger 2 switches to the initial state of trigger 4 and the trigger 3 is initialized. The output pulse on bus 11 ends and the device is brought to its initial state.

If the control pulse on bus 6 has not yet ended, switching of trigger 2 does not occur. When entering the next synchro bus 8

The triggering pulse 4 is switched by the trigger 4. A low potential is set at its inverse output, and a high potential from which the trigger 3 is triggered at the forward pulse, and the output pulse on the bus 11 ends. At the same time, a high potential from the direct output of the trigger 4 passes to the output of the element 5 and switches the counter 1 to the subtraction mode. The following described process of forming pulses on the output busbar 11 is repeated.

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Thus, when a control pulse arrives on the busbar 6 on the bus 11 with a delay determined by the; A coherent code on the tires 9. a series of pulses is formed, with the number of pulses of the series proportional to the duration of the control pulse.

Claims (1)

Invention Formula A device for forming a series of pulses containing two flip-flops, an And element and a pulse counter, the recording input of which is connected to the output of the And element, and the information inputs are connected to the code bus, the C input of the first trigger is connected to the synchronization bus, and the output of the second trigger is connected to the output chic, characterized in that, in order to increase reliability and noise immunity, a trigger is additionally introduced in it, the S input of which is connected to the reset bus, and the inverse output is connected to the L input of the first trigger of the element I and the R input of the second trigger, the counting input of which is connected with another input of the input AND and the direct output of the first trigger, the D input of which is connected to the transfer output of the pulse counter, and the inverse output connected to the C input of the additional trigger, D and To the inputs of which are connected to the control bus and the clock bus is connected to the counting input of the pulse counter. 45 50