SU1757092A1 - Device for shaping single pulse - Google Patents

Abstract

The essence of the invention: the device contains 4 RS-flip-flops 1,4,7,10,5 elements AND-NOT 13, 14, 15, 16, 17, inverter 18, clock bus 19, control signal bus 20, output bus 21 with corresponding links. 3 il.

Description

The invention relates to a pulse technique and can be used in automation devices and computer engineering, in particular in synchronization devices.

A number of devices are known for generating or isolating single pulses.

However, these devices have low reliability.

A device for generating a single pulse containing a control signal bus, a clock bus, three asynchronous installation triggers on two AND-NOT elements each, the clock bus is connected to the unit setting input of the first trigger and the zero setting input of the second trigger, the zero output of which is connected to the output of the device and with the input of the zero setting of the third trigger. Device it also contains an OR circuit, the first input of which is connected to the zero output of the third trigger, the second input is to the control signal bus, the output is to the second input of the second trigger zero.

The rather high reliability of this device is due to the fact that it does not go astray when there are short interference pulses on the control signal bus both at zero and at a single signal on the synchronizing pulse bus. However, this device has a time interval in which the device responds to an interfering signal on the control bus and causes a false formation of a single pulse at the output. to the bus. The presence of this interval reduces the reliability of this device.

A device for generating a single pulse containing a control bus, a clock bus, an output bus, four asynchronous installation triggers on two Y-NOT elements each, five NAND elements, an inverter, while the clock pulse is connected to the first input of the first AND element -NOT, with the S-input of the first trigger, with the first input of the second AND-NOT element and with the R input of the second trigger, whose inverse output is connected to the output bus and with the S-input of the third trigger, the control signal bus is connected to the the input of the third AND-NOT element, with the second input of the second AND-NOT element and with the first input of the fourth AND-NOT element, the output of which is connected to the R-input of the third trigger and with the first input of the fifth AND-NOT element, the output of which is connected to S the input of the second trigger and the second input of the first AND-NOT element, the output of which is connected to the second input of the third AND-NOT element, the output of which is connected to the R-bhod of the fourth trigger, the S-input of which is connected to the second input of the fifth AND-NOT element and with direct output of the first trigger, whose inverse output is connected ene with a third input of the second AND-NO element, Rvhod - with direct access to the fourth flip-flop, the inverse output of the third flip-flop is connected to the third input of the fifth AND-member,

This device has high operational reliability, which is ensured by eliminating false positives from single interference (emissions) of any polarity that do not coincide with the leading edge of the clock. This property allows the device to be used in synchronization units, which are controlled from signals with a high level of interference and interference.

However, the reliability of this device is limited due to the presence of competitions on the fronts of impulses.

The purpose of the invention is to increase the reliability by completely eliminating competitions on the fronts of pulses.

This goal is achieved by the fact that in a device for forming a single pulse, containing a control bus, a clock bus, an output bus, four asynchronous installation triggers on two AND-NOT elements each, five AND-NOT elements, an inverter, while the clock pulse bus is connected with the first input of the first AND-NOT element, with the S-input of the first trigger, with the first input of the second AND-NOT element and with the R-input of the second trigger, the inverse output of which is connected to the output bus and with the S-input of the third trigger, the control signal bus through the inverter is connected to the first input of the third AND-NOT element, with the second input of the second AND-NOT element and to the first input of the fourth AND-NOT element, the output of which is connected to the R-input of the third trigger and the first input of the fifth AND-NOT element which is connected to the S-input of the second trigger and to the second input of the first AND-NOT element, the output of which is connected to the second input of the third AND-NOT element, the output of which is connected to the R-input of the fourth trigger, whose input is connected to the second input of the fifth AND element NOT and with direct output of the first trigger the inverse output of which is connected to the third input of the second AND-NOT element, the R-input is with the direct output of the fourth trigger, 'the inverse output of the third trigger is connected to the third input of the fifth AND-NOT element. the second input of the fourth AND-NOTH element is connected to the inverse output of the third trigger, the additional R-input of which is connected to the output of the second AND-NOT element and to the fourth input of the fifth ITN-NOT element, the output of which is connected to the additional S-input of the first trigger.

In FIG. 1 shows a circuit diagram of the proposed device for the formation of a single pulse; in FIG. 2 and 3 are timing diagrams of the operation of the device.

The noise arising on the control signal bus and the reaction of the circuit elements caused by these noises are conditionally shaded.

The device comprises a first trigger 1, consisting of AND-NOT 2 and 3 elements; the second trigger 4, consisting of the elements NAND 5 and 6; the third trigger 7, consisting of AND-NOT elements 8 and 9; the fourth trigger 10, consisting of the elements AND NOT 11 and 12; first Element NAND 13; the second element is NOT 14; the third element is NAND 15; the fourth element AND 16; fifth element AND NOT 17; inverter 18; a bus of 19 clock pulses; a bus 20 of control signals; output bus 21.

In this case, the clock bus 19 is connected to the S-input of the first trigger 1 and the R-input of the second trigger 4, the inverse output of which is connected to the output bus 21 and the S-input of the third trigger 7, the bus 20 of the control signals is connected to the input of the inverter 18, the output of which connected to the first input of the first AND-NOT 13 element, the second input of which is connected to the output of the second AND-NOT 14. element and the output to the R-input of the fourth trigger 10, whose direct output (the output of the AND-NOT 11 element) is connected to R- the input of the first trigger 1, the inverse output of which (the output of the element AND-NOT 3) sub is connected to the first input of the third AND-NOT 15 element, the second input of which is connected to the output of the inverter 18, and the third input is to the first input of the second AND-NOT 14 element and the R-input of the second trigger 4, whose input is connected to the second input of the second AND element -NE 14 and the output of the fourth AND-NOT 16 element, the first input of which is connected to the direct output of the first trigger 1 (the output of the AND-NOT 2 element) and the S-input of the fourth trigger 10, and the second input is connected to the inverse output of the third trigger 7 ( the output of the AND-NOT element 8), the R input of which is connected to the third input of the fourth electric of the AND-NOT element 16. The first input of the fifth AND-NOT 17 element is to the second input of the third AND-NOT 15 element, the output of which is connected to the R-input of the third trigger 7, the additional R-input of which is connected to the output of the fifth AND-NOT 17 element and the fourth input of the fourth AND-NOT 16 element, the second input of which is connected to the second input of the fifth AND-NOT 17 element, and the output is connected to an additional S-input of the first trigger ....... .....

The device operates as follows. : -

Suppose that at the initial moment before applying the first pulse to bus 19 on bus 20 there is a positive (unit) potential, at the zero output of trigger 3 (output of AND-NOT 9 element) and a single output of trigger 4 (output of AND-NOT 11 element) risutst'öue ^^ Dy'y'Zh''1y p ot n e tial; Zero potential on the bus The input provides the formation of single signals at the outputs of the AND-NOT 2, 6 elements. 14, Zero signal at the output of the inverter 18 provides the appearance of 'single signals at the outputs of the AND-NOT 17, 13, 15. At all inputs of AND elements - NOT 3,8,12 are single signals, which leads to the formation of zero signals at their outputs. The zero signal at the output of the AND-NOT 8 element determines the formation of a single signal at the output of the AND-NOT 16. This signal is fed to the input of the AND-NOT 5 element, on which both inputs are single signals, which ensures that a zero signal appears at its output. Thus, all output signals of the device are initially determined.

At the time to the beginning of the pulse on the bus 19 at both inputs of the AND-NOT 14 element are single signals, and a zero signal is generated at its output. The remaining signals at the outputs of the logic elements at the time to remain unchanged.

At the time ti of the appearance of a zero signal on the control bus 20, a single signal appears at the output of the inverter 18. The remaining signals at the outputs of the logic elements at time ti remain unchanged.

Under the influence of interference at a time between ti and t2, the interference signal appears only at the output of the inverter 18, another reaction of the device to the influence of interference is not observed, the output signal of the device does not change.

At the moment t2 of the end of the pulse on the bus 19 at the output of the AND-NOT 14 element, a single signal appears. This signal is fed to the input of the AND-NOT 13 element, at the other input of which a single signal is also present. This determines the formation of a zero signal at the output of the AND-NOT 1 3 element. This zero signal switches the trigger 10, while a single signal is generated at the output of the AND-NOT 12 element, and zero at the output of the AND-NOT 11 element, which, in its in turn, forms a single signal at the output of the AND-NOT 3. element. The remaining signals at the outputs of the logic elements at time t2 remain unchanged.

Under the influence of interference in the period between t2 and 1s, the interference signal appears at the output of the inverter 18 and at the output of the AND-NOT 13 element in the form of a single short signal. After the cessation of interference, the signals at the outputs of these elements return to their original state. The output signal of the device does not change.

At the moments of the beginning of the pulse on the bus 19 at all inputs of the elements AND-NOT 2, 14 and 15 are single signals, which leads to the formation of the outputs of these elements of zero signals. A zero signal at the output of the AND-NOT 2 element confirms a single signal at the output of the AND-NOT 1bi element switches trigger 10, while a single signal appears at the output of the AND-NOT 11 element, and zero at the output of the INE 12 element. The zero signal at the output of the AND-NOT 14 element generates a single signal at the output of the AND-NOT 13 element. The zero signal at the output of the AND-NOT 15 element switches trigger 7, while a single signal appears at the output of the AND-NOT 8 element, and the output of the element AND NOT 9 - zero. At both inputs of the AND element, single signals are shown, as a result of which a zero signal is generated at its output. The remaining signals at the outputs of the logic elements at the moment 1c remain unchanged. . *

When exposure to noise in the period between gs and And, the interference signal appears at the output of the inverter 18 And at the outputs of the AND-NOT elements 15 and 17. After the termination of the interference, the signals at the outputs of these elements return to their original state. The output signal of the device does not change.

At the moment of the end of the pulse on the bus 19 at the outputs of the elements AND-NOT 2, 14 and 15 appear single signals. A single signal from the output of the AND-NOT 14 element is fed to the input of the AND-NOT 13 element, while at the both inputs of the latter there are single signals, and the output is a zero signal, which, in turn, switches trigger 10, while at the output of the element AND-NO 12 a single signal appears, and at the output of the AND-NOT 11 element - zero. It should be noted that at the output of the AND-NOT 3 element, a short negative (zero) impulse may appear, caused by the operation of this element first from the element

AND-NOT 2 and returning to the initial state after switching trigger 10 (from the zero signal of the AND-NOT 11 element). This short pulse does not affect the output signal of the device. The remaining signals at the outputs of the logic elements at the time x ^ remain unchanged.

Under the influence of interference on the time interval between t4 and is, the interference signal appears at the output of the inverter 18. at the outputs of the NAND elements 13 and 17 in the form of a short single signal. The interference signal at the output of the AND-NOT 17 element leads to interference at the output of the AND-NOT 16 element in the form of a short zero signal, which, in turn, leads to the short-term occurrence of a single signal at the output of the AND-NOT 5. In this case, trigger 4 doesn't switch like that. as at the input of the AND-NOT 6 element there is a zero signal from the bus 19. After the cessation of interference, the signals at the outputs of all these elements return to their original state. The output signal of the device does not change.

At the moment ΐς of the beginning of the pulse, on the bus 19, all inputs of the AND-NOT 2, 14, and 15 elements have single signals, which leads to the formation of zero signals at the outputs of these elements. The zero signal at the output of the AND-NOT 14 element determines the formation of a single signal at the output of the AND-NOT 13 element. The zero signal at the output of the AND-NOT 2 element switches trigger 10, while a single signal appears at the output of the AND-NOT 11 element, and the output element AND NOT 12 - zero. The remaining signals at the outputs of the logic elements at the time is remain unchanged.

At the time to the end of the zero pulse on the bus 20 at the output of the inverter 18, a zero signal appears, which generates single signals at the outputs of the AND-NOT elements 17 and 15 and confirms a single signal at the output of the AND-NOT 13. Other signals at the outputs of the logic elements at the time 16 remain unchanged.

When exposure to noise in the period between t6 and t7, the interference signal appears at the output of the inverter 18 in the form of a short single signal and at the outputs of the AND-NOT 17 and 15 elements in the form of a short zero signal. In this case, trigger 7 does not switch, i.e. at the input of the AND-NOT element 8 there is a zero signal from the output of the AND-NOT element 9. After the cessation of interference, the signals at the outputs of the AND-NOT elements 17 and 15 and the inverter 18 are returned to their original state. The output signal of the device does not change.

. At the time t7 of the end of the pulse on the bus 19 at the outputs of the elements AND-NOT 2 and 14 appear single signals. Moreover, at all the inputs of the AND-NOT 3 and 16 elements, single signals appear, which determines 5 the formation of zero signals at their outputs. The zero signal at the output of the AND-NOT 16 element leads to the appearance of a single signal at the output of the AND-NOT 5. The remaining signals at the outputs of the logical 10 elements at time t7 remain unchanged.

Under the influence of interference in the interval between t7 and te, the interference signal appears at the output of the inverter 18 and at the output 15 of the AND-NOT 13 element in the form of a short zero pulse. This short pulse triggers trigger 10 with its leading edge, while a single signal appears at the output of the AND-NOT 12 element, and a zero signal at the output of the .20 AND-NOT 11 element, which, in turn, determines the formation of a single signal at the output of the INE element 3. After the cessation of signal interference on the inverter 18 and the NAND element 13 returns to its original state. Elements INE 11 and 12 do not return to their original state after exposure to interference, however, this does not affect the output signal, which remains unchanged. thirty

At the moment t8 of the beginning of the pulse, on the bus 19, all inputs of the AND-NOT 6 element turn out to be single signals, which determines the appearance of a zero signal at its output, which is the output signal of the device. This zero signal switches * trigger 7, while at the output of the And ^: NOT 9 element a single appears, and at the output of the And-NOT 8 element, a zero signal that generates a single signal at the output 40 of the And-NOT 16. At the same time, at all inputs elements AND-NOT 2 and 14 are single signals, which leads to the formation at the outputs of these elements of zero signals. The zero signal from the output of the AND-45 NOT 2 element switches the trigger 10. At the same time, a single signal appears at the output of the AND-NOT 11 element, and the zero signal appears at the output of the AND-NOT 12 element. It should be noted that the effect of the interference that passed in the interval between t7 and ΐβ is terminated. The remaining signals at the outputs of the logic elements at time ts remain unchanged.

When interference occurs in the interval 55 times between te and tg, the interference signal appears at the output of the inverter 18 and at the output of the AND-NOT 15 element in the form of a short zero pulse, which, in turn, leads to the appearance of a short single pulse at the output of the AND-NOT element 8. During the action of a pulse, single inputs appear at both inputs of the AND-NOT 17 element, as a result of which a zero pulse is generated at its output. After the termination of the interference, the signals at the outputs of all elements return to their original state. The interference does not affect the output signal, and for a given period of time, the formation of a single output pulse continues at the output of the NAND 6 element (output bus 21).

At the moment tg of the end of the pulse on the bus 19, the trigger 1 is switched, at the same time a single signal appears at the output of the AND-NOT 2 element, and zero at the output of the AND-NOT 3 element, and the formation of the output pulse at the output of the AND-NOT 6 element ends where a single signal appears. The remaining signals at the outputs of the logic elements at time tg remain unchanged.

Consider the appearance of interference in the time interval between t9 and over, i.e. after the formation of a single pulse at the output of the device. When an interference occurs, the interference signal appears at the output of the inverter 18 and at the input of the AND-NOT 13 element in the form of a short zero pulse that switches the trigger 10, while a single signal appears at the output of the AND-NOT 12 element, and at the output of the AND-NOT 11 element a zero signal, which, in turn, generates a single signal at the output of the NAND 3 element. After the cessation of interference, the output signals on the inverter 18 and the NAND 13 element return to their original state. The trigger 10 remains in the switched State, and a single signal remains at the output of the AND-NOT 3 element. However, this does not affect the output signal, which remains unchanged.

At the moment of the beginning of the pulse on the input bus, all the inputs of the AND-NOT 2 and 14 elements have single signals, which ensures the formation of zero signals at the outputs of these elements. The zero signal at the output of the AND-NOT 2 element switches trigger 10, thereby removing the reaction from the effects of interference. In this case, a single signal appears at the output of the AND-NOT 11 element, and zero at the output of the AND-NOT 12 element. The remaining signals at the outputs of the logic elements at the time tio remain unchanged.

At the moment tn of the end of the pulse, on the outputs of the AND-NOT 2 and 14 elements, single signals appear. At the same time, single signals appear at both inputs of the AND-NOT 3 element, which ensures the formation of a zero signal at its output. The remaining signals at the outputs of the log elements at the time tn remain unchanged.

At the moment 112 of the beginning of the negative signal on the bus 20. control at the output of the inverter 18 appears a single signal. In this case, single signals appear at both inputs of the AND-NOT 13 element, which leads to the formation of a zero signal at its output, which switches trigger 10, while a single signal appears at the output of the AND-NOT 12 element, and the output of the AND-E element 11 - a zero signal, which, in turn, leads to the appearance of a single signal at the output of the AND-NOT 3. element. The remaining signals at the outputs of the logic elements at the time ig remain unchanged.

When exposure to interference in the time interval between ti2 and From, an interference signal appears at the output of the inverter 18 and the output of the AND-NOT 13 element. After the termination of the interference, the signals at the outputs of these elements return to their original state. The output signal of the device remains unchanged.

At the moment 113 of the onset of the pulse on the bus 19, the operation of the device completely repeats the work described at the time of the MS.

When exposure to interference in the time interval between PZ.PD interference signal appears at the output of the inverter 18 and the outputs of the elements AND-NOT 15 and 17. After the termination of the interference signals at the outputs of these elements return to their original state. The output signal of the device remains unchanged. .

At the moment 114 of the end of the pulse on the bus 19, the operation of the device completely repeats the work described at time t4.

At the moment 115 of the end of the negative pulse on the bus 20 at the outputs of the AND-NOT 13 and 17 elements, single signals are formed. At the same time, all the inputs of the AND-NOT 16 element have single signals, which leads to the formation of a zero signal at its output, which, entering the input of the AND-NOT 5 element, forms a single signal at its output. The rest of the signals at the outputs of the logic elements at the time w remain unused.

When exposure to interference in the interval between 115 and 116, the interference signal appears on the inverter 18 and the elements AND 13 and 17 in the form of zero short pulses.

A zero short pulse at the output of the AND-NOT 17 element leads to the appearance of a single pulse at the output of the AND-NOT element

16. At the same time, single signals appear at both inputs of the AND-NOT 5 element, and a short negative pulse is formed at its output. After the cessation of interference, the signals at the outputs of all these signals return to their original state. The output signal of the device remains unchanged.

At the moment of beginning of the tie on the bus 19, the operation of the device completely repeats the operation described at time t8.

At the moment 117 of the end of the pulse on the bus 19, the operation of the device completely repeats the work described at time tj. .

At the moment tis of the beginning of the pulse, on the bus 19, all the inputs of the AND-NOT 14 element contain single signals, which leads to the appearance of a zero signal at its output. The remaining signals at the outputs of the logic elements at time tis remain unchanged.

When exposure to interference in the interval between hu and 119, the interference signal appears only at the output of the inverter 18. After the termination of the interference, the output signal of the inverter returns to its original state. The output signal of the device remains unchanged.

At the instant Pe of the end of the pulse on the bus 19 at the output of the I-HE14 element, a single signal appears. The remaining signals at the outputs of the logic elements at time 119 remain unchanged.

At the moment t20 of the beginning of the pulse, single signals appear on the bus 19 at both inputs of the AND-NOT 14 element, as a result of which a zero signal is generated at its output. The remaining signals at the outputs of the logic elements at time t2o remain unchanged.

At the time tai of the beginning of the interference on the bus 20, the interference signal appears only at the output of the inverter 13. The remaining signals at the outputs of the logic elements remain unchanged.

At the moment t22 of the end of the pulse on the bus 19 during the influence of interference on the bus 20, a single signal appears at the output of the AND-NOT 14 element, which gets to the input of the AND-NOT 13 element. In this case, single signals appear at both inputs of the latter, which leads to the formation of at its output there is a zero signal, which triggers trigger 10. At the output of the AND-NOT 12 element, a single signal appears, and at the output of the AND-NOT 11 element, a zero signal, which, in turn, forms a single signal at the output of the AND-NOT 3 element. The rest of the signals on you13

1757092 The 14 moves of the logic elements remain unchanged.

At the moment 123 of the end of the interference signal on the bus 20 at the output of the inverter 18, a zero signal appears, which generates a 5 unit signal at the output of the AND-NOT 13 element. The rest of the signals at the outputs of the logic elements at the same time remain unchanged.

At the moment t24 of the beginning of the pulse, on the bus 10 19, all the inputs of the AND-NOT 2 and 14 elements have single signals, which determines the appearance of zero signals at the outputs of these elements. The zero signal from the output of the AND-NO 2 element triggers the trigger 15 ger 10, while a single signal appears at the output of the AND-NOT 11 element, and the zero signal at the output of the AND-NO 12 element. In this case, the reaction of the effect of interference on this trigger is removed. The remaining signals at the 20 outputs of the logic elements at time t24 remain unchanged.

At the moment t25 of the end of the pulse, a single signal is generated at the output of the AND-NOT 14 element and 25 trigger 1 is switched. At the same time, a single signal appears at the output of the AND-NOT 2 element, and a zero signal is output at the output of the AND-NOT 3 element. It should be noted that in this case, the reaction from the influence of interference 30 that has passed in the time interval from ΐ? Ι to t23 is completely removed. The remaining signals at the outputs of the logic elements at time t25 remain unchanged.

At the moment t26 of the beginning of the negative 35 signal on the bus 20, the operation of the device completely repeats the operation described at time Ϊ12.

At the moment ΐ27 of the beginning of the pulse on the bus, the operation of the device completely repeats 40 the work described at time t3; at the moment ΐ28 of the end of the pulse on the bus 19, the operation of the device completely repeats the work described at time t4. . _s

At the moment t29 of the beginning of the pulse on the bus 45 19, the operation of the device completely repeats the operation described at time ts.

At the moment of the start of the noise signal on the bus 20, a zero signal appears on the output of the inverter 18, which generates the same 50 signals at the outputs of the AND-NOT elements 15 and 17. The remaining signals at the outputs of the logic elements at the time of the start-up remain unchanged.

At the moment t3i of the end of the pulse on the 55 bus 19 (during the action of interference on the bus 20), a single signal appears at the output of the AND-NOT 14 element and the trigger 1 is switched, while at the output of the element

AND NOT 3 zero signal. At all the inputs of the AND-NOT 16 element there are single signals, which leads to the appearance of a zero signal at its output. The remaining signals at the outputs of the logic elements at time tai remain unchanged.

At the time of the end tag interference signal at the output of the inverter 18 appears a single signal. At the same time, all 10 inputs of the AND-NOT 13 and 17 elements are unit 10 signals, as a result of which zero signals appear at the outputs of these elements. The zero signal from the output of the AND-NOT 17 element generates a single signal at the output of the AND-NOT 16 element, while on all inputs 15 of the AND-NOT 5 element there are single signals, and a zero signal appears at its output. The zero signal from the output of the AND-HE 13 element switches the trigger 10, while a single signal appears at the output of the AND-HE 12 element, and a zero signal appears at the output of the AND-HE 11 element, which, in turn, generates a single signal at the output element AND NOT 3.

It should be noted that at this moment 25, the reaction is completely removed from the influence of interference that has passed in a period of time from ΐ30 to t32 · The remaining signals at the outputs of the logic elements at time t32 ~. remain unchangedG '’* ^^

At the moment of start of the pulse on the bus 19, the operation of the device completely repeats the work described at time ts.

At the moment t34 of the end of the pulse, the operation on device 35 is not 19, the operation of the device completely repeats the operation described at time t4.

In the process of describing the work, all possible cases of the appearance of interference on the bus 20 are considered (except for interference 40 coinciding with the leading edge of the clock pulses). The device reliably eliminated all interference signals. During operation of the device a single time _s is not recorded by the presence of competition impul45 fronts owl. Therefore, the device is highly reliable in operation.

Claims (1)

Claim A device for generating a single pulse containing a control bus, a clock bus, an output bus, four asynchronous installation triggers on two Y-NOT elements each, five I-NOT elements, an inverter, while the clock pulse bus is connected to the first input of the first element -NOTE, with S-bxo- ~ the house of the first trigger, with the first input of the second AND-NOT element and the R-input of the second trigger, whose inverse output is connected to the output bus and to the S-input of the third trigger, the control signal bus is connected to the inverter with first entry ohm of the third AND-NOT element, with the second input of the second AND-NOT element and with the first input of the fourth AND-NOT element, the output of which is connected to the R-input of the third trigger and with the first input of the fifth AND-NOT element, the output of which is connected to S- the input of the second trigger and the second input of the first AND-NOT element, the output of which is connected to the second input of the third AND-NOT element, the output of which 10 is connected to the R-input of the fourth trigger, the S-input of which is connected to the second input of the fifth AND-NOT element and with direct output of the first trigger, the inverse output of which is connected to the third input of the second AND-NOT element, the R-input - with the direct output of the fourth trigger, and the inverse output of the third trigger is connected to the third input of the fifth element 5 AND-NOT, characterized in that, in order to increase reliability in operation by completely eliminating competitions in to the pulse fronts, the second input of the fourth AND-NOT element is connected to the inverse output of the third trigger, the additional R-input of which is connected to the output of the second AND-NOT element and to the fourth input of the fifth AND-NOT element, the output of which is connected to the additional S-input first trigger15 ra. FIG. 3 Editor V. Danko Compiled by V. Fungus Tehred M. Morgenthal Corrector S. Yusko Order 3099 Circulation Subscription. VNIIIPI State Committee for Inventions and Discoveries under the State Committee for Science and Technology of the USSR 113035, Moscow, Zh-35, Raushskaya nab .., 4/5 Production and Publishing Combine Patent, Uzhgorod, 101 Gagarin St.