SU1541777A1 - Divider of pulse frequency by five - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing. The purpose of the invention — an increase in the reliability of the device — is achieved as a result of the introduction of new connections, which exclude failures in the operation of the device. The device contains a single-stroke T-flip-flop 1, a push-pull T-flip-flop 2 with overlapping beats, an asynchronous RS-flip-flop 3, three AND-NES 4,5,6 elements, an input bus 7 of the device and a bus 8 for setting the initial state of the device. A single-stroke T-flip-flop 1 contains six AND-HE elements 9-14, a push-pull T-flip-flop 2 contains five AND-NE elements 15-19, the RS-flip-flop 3 contains two IS-HE elements 20 and 21. 2 ill.

Description

1

The invention relates to a pulse technique and can be used in automation and computing.

The aim of the invention is to improve the reliability of the device by introducing new connections, eliminating failures of the device,

Fig. 1 shows a structural-electrical divider circuit; Fig. 2 shows timing diagrams for the operation of the divider.

The frequency divider with / keeps one-stroke T-trigger 1s push-pull T-trigger 2 with overlapping cycles, asynchronous RS-trigger 3, first 4, second 5 third 6 AND-HE0 elements

The synchronous input of the one-stroke T-flip-flop is connected to the input bus 7 of the device and the first input of the first NAND 4, and the inverse output and the inverse of the delayed output are connected respectively to the first and second synchronization inputs of the push-pull T-flip-flop 4 is connected to the output of the second element AND-NOT 5E and the output to the first information input of the one-cycle T-flip-flop 1s, the first input of the second AND-NEF 5 element and the first input of the O-flip-flop 30 setting

The second input of the second element AND-NOT 5 is connected to the second information input of the one-touch T-flip-flop 1 and the output of the third element of the IS-NOT 6, the first input of which is “,., Is connected with the direct output of the RS-flip-flop 3, and the second input is with an installation input of 1 RS flip-flop 3 and an output of push-pull T-flip-flop 2,

The input 8 of the setup of the initial state of the device is connected to the inputs of the installation

the second input of the gera 3 installation, with the second input of the second element AND-NOT 5, the first input of the third element AND-NOT is connected to the direct output of the RS flip-flop 35 the installation input in 1 of which is connected to the second input of the third element AND-NOT 6 and the crack input second T-flip-flop 2 "First T-flip-flop 1 contains six AND-NOT elements; second T-flip-flop 2 contains five AND-NOT elements 15-19; RS-flip-flop H contains two AND-NOT elements 20 and 21. Instead of AND elements - It is not possible to use the elements OR NOT

About T-flip-flops 1 and 2 and with

About RS Trig

five

The divider works as follows

Before applying the input positive pulses, all the triggers of the divider are set to state O (the outputs of the elements 13, 18, and 21 are the direct outputs of the triggers).

With the arrival of the first positive

pulse (moment t,) to the input of the divider 7, at the output of the element 10 a zero signal is generated, which generates single signals at the outputs of elements 12, 13 and 160 At the time tz the signal

5 at the output of the element 10 becomes

unit, which causes the presence of single signals at the inputs of element 9. This leads to the appearance of a zero signal at the output of element 9 “Other

0 changes in the output signals of the elements at the time ty does not occur. Thus, after the first pulse, the number 101 appears in the divider.

With the arrival of the second pulse (time tj), all the inputs of the element 11 produce single signals, and a zero signal appears at its output, which causes the appearance of a single signal at the output of the 14 "element. After that, all the inputs of the element 13 receive single signals, and a zero signal is generated at its output. The remaining output signals of the logic elements remain unchanged until the moment t of the end of the second pulse, At the moment t,). the signal at the output of element 11 becomes single. As a result, single signals are generated at all inputs of element 12, and a zero signal is generated at its output, resulting in a single signal at output of element 9. After that, single signals are output to all inputs of element 15 and A zero signal appears at the output, which transfers element 18 to state 1. After that, all inputs of element 19 are single signals, as a result of which a zero signal is generated at its inputs, which translates element 17 to state 1 After that, all inputs of element 6 are single signals, and a signal is generated at its output. Signal O At element 6 output, element 5 is switched to state 1. Other changes in the signals at the element outputs at time t & not happening,

0

0

and in the frequency divider is the number of software.

With the arrival of the third pulse (time tj), all the inputs of element 4 turn out to be single signals, which leads to the appearance of a zero signal at its output, which sets element 1 to a state. The zero signal at the output of element 4 confirms the single signals at the outputs of elements 5 and 10 "After that, all the inputs of element 21 have a single signal, which causes the appearance of a zero signal at its output. This signal is set to state 1 element 6" Then, during the third pulse, the signals at the outputs of the elements Ithel frequency pulses into five ostanuts unchanged at the time t after the third pulse at the output member 4 is of a single signal, and all the inputs member 5 okazyvayuts unit signals thus generated at the output 5 signal of the zero element. There are no other changes in the signals at the outputs of the elements of the pulse frequency divider by five at the instant tg, and the number 010 appears in its triggers at the end of the third pulse.

With the arrival of the fourth pulse (time tt), all the inputs of the element 10 produce single signals, which leads to the appearance of a zero signal at its output. This signal confirms single signals at the outputs of elements 9 and 11 and sets element 1 to state 1. After this, single signals appear at all inputs of element 14, and a zero signal appears at its output. It confirms a single signal at the output element 1 b and sets elements 1 and 12 to state 15. The remaining output signals of the elements remain unchanged until the moment te ends of the fourth pulse. At time t8, a single signal is generated at the output of element 10, and all the inputs of element 9 have single signals at its output a zero signal is generated. There are no other changes in signals at time t8 and the number 011 appears in the divider,

With the arrival of the fifth positive impulse (moment t9), all inputs of the element 11 are single

0

five

signals, and a zero signal is generated at its output. It confirms a single signal at the output of element 12 and causes the appearance of a single signal at the output of element 14. After that, all the inputs of elements 13 and 16 have single signals, and zero signals are generated at their outputs. The zero signal at the output of the element 16 confirms the single signal at the output of the element 17 and sets in one state the signal at the output of the element 19. As a result, single inputs are generated at all inputs of the element 18, and a zero signal is formed at its output t, e termination of the nth pulse. At time 0 t, 0, the signal at the output of element 1 1 is made single and at all inputs of element 12 there are single signals. The output of element 12 is a zero signal, which causes the appearance at element 9 of a single signal. No other signal changes at time t10 occur. At time t, 0, the output signals of the pulse frequency divider by five repeat the output signals before the first pulse is applied. Obviously, the operation of the pulse frequency divider by five is repeated.

To set the triggers 1–3 of the pulse frequency divider to five in the initial zero state, a zero signal is sent to the bus 8, preceding the divider input pulses in time.

five

0

five

0

Claims (1)

Invention Formula A pulse frequency divider for five that contains a single-cycle T-trigger, whose synchronization input is connected to the device input bus, and the first and second inverse outputs are connected to the first and second synchronous inputs of a push-pull T-trigger with overlapping clocks, respectively, asynchronous RS -the trigger and the first, second and third elements NAND, the first input of the first element NAND is connected to the input bus of the device, the second input is connected to the output of the second NAND element, and the output is connected to the first input of the second NAND element and the first installation entrance in About RS flip-flop, the output of the third element F - HE is connected to the first information input of the one-cycle T-flip-flop, the installation inputs in O of the one-stroke and push-pull with the switching cycles of the T-flip-flop and RS-flip-flop are connected to the second input of the O setting of the RS-flip-flop and the installation input of the initial state devices, about tl is that to improve reliability the divider due to the possibility of preventing failures, the output of the first NAND element is connected to the second information input of the one-cycle T-flip-flop, the first input of the third NI element is connected to the direct output of the RS flip-flop, and the second input is connected to the input of installation 1 RS-flip-flop and the output of the push-pull T-flip-flop, and the output - with the second input of the second NAND element. t, tt kn t9ts n8 t $ tm