SU544115A1 - Clock synchronization device - Google Patents

Description

(54) DEVICE OF CLOCK SYNCHRONIZATION

one

The invention relates to a pulse technique and can be used in various devices for converting, processing and transmitting information,

The known device contains triggers, logical elements AND-NOT and pulse shapers l.

The disadvantage of this device is the complexity of the circuit and, as a result, low speed.

The closest technical solution to this invention is a clock synchronization device containing two successively connected flip-flops, an IS-NOT element, the first input of which is connected to the clock input of the first flip-flop, the second input of the NAND element is connected to the single output of the first flip-flop 2.

However, besides the main impulse, at the output of this device a part of the second impulse (interferer) is made, according to the duration of the wound response time of the second trigger, which leads to false triggering of subsequent devices.

The aim of the invention is to increase the resistance of the device.

To do this, in a clock synchronization device containing two series-connected flip-flops, an IS-NOT element, the first input of which is connected to the clock input of the first trigger, the second input of the INE element is connected to the unit output of the first trigger, the zero output of the first trigger is connected to, the clock input of which is connected to the output of the NAND element, and the single output of the second trigger is connected to the third input of the NAND element.

The drawing shows a diagram of the device.

The clock synchronization device contains the triggers 1 and 2, the element IS-NOT 3, the clock input 4, the control input 5 and the output 6, and the inputs 4 and 5 are connected respectively to the clock input of the trigger 1 connected to the first input of the element 3 and the zero input trigger 1, connected to its information input, single and zero outputs of trigger 1 are connected respectively to the second input of element 3 connected to the single input of trigger 2, and information input of trigger 2, the output output of which is connected to the third input of element 3, which outputs It is connected to clock input trigger 2 and output 6. The device operates as follows. Initially, the zero potential at input 5 sets a zero potential at the single output of trigger 1, which prevents the passage of clock signals through element 3, and also sets at the output of trigger 2 single potential. When a single potential is applied to the input 5, trigger 1 is prepared for operation. FIoot the clock signal after this, the leading edge throws trigger 1 and the unit potential from its output to the second input of element 3 allows the clock signal to flow to the first input of element 3. In addition, from zero output of trigger 1 the zero potential enters the information trigger input 2 and prepare it to work. The generated signal from the output of the element 3, arriving at the clock input of the trigger 2, the rear edge throws it. At the same time, the zero potential from the output of the trigger 2 is fed to the third input of the element 3 and prohibits

Claims (2)

t prevents further clock flow. The device returns to its original tuning when it is removed from input 5 of a single potential. Claim synchronization device containing two series-connected flip-flops, an IS-NOT element, the first input of which is connected to the clock input of the first flip-flop, the second input of the NAND element is connected to the single output of the first flip-flop, in order to improve the noise immunity of the device , in it the zero output of the first trigger is connected to the information input of the second trigger, the clock input of which is connected to the output of the NAND element and the single output of the second trigger is connected to the third course of AND-NO element, sources of information received note in the examination: 1.Avtorskoe № Certificate USSR 453,791, 03 ul H 5 K / 153,30.07.73. 2. Gutnikov V.S. Integral electronics in measuring devices. L., Energie, 1974., p. 114, fig. 61 (prototype).