SU1285577A1 - Synchronizing device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention, to increase the noise immunity, is achieved in that the device does not respond to the duration of the input pulses of less than two periods of the clock frequency. For this purpose, a delay element, a fourth coincidence element, an IGSH-NOT element, a fourth trigger, and a one-oscillator are added to the device. The drawing shows a pulse counter 1, triggers 2, 3, 4 and 5, elements 6, 7, 8 and 9 coincidence, the element OR-NOT 10, the element I delay, the one-shot 12, the bus clock pulse control pulses 13, 14 and the output 15. The first 6 and fourth 9 elements of the match are AND elements, the second 7 and third 8 elements of the match are NAND elements. 1 il. J 0

Description

The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to increase the space j of protection, which consists in the absence of response to the duration of the input pulses, which is shorter than the two periods of the clock frequency. 10

The drawing shows the electrical functional diagram of the synchronization device.

The synchronization device contains J5 pulse counter 1, the first 2, the second 3, the third 4 and the fourth 5 triggers, the first 6, the second 7 the third 8 and the fourth 9 match elements, the element OR-NOT 10, the element 11 delay-2o ki, the one-shot 12, the clock bus 13, the control bus 14 and the output bus 15, wherein the clock input of the pulse counter 1 is connected to the output of the OR-NOT 10 element, the first 25 input of which is connected to the reset input of the pulse counter 1, to the reset input of the second trigger 3, fifth the output of which is connected through the one-shot 2 to the output bus 15 and c in S - 30 with the stroke of the third coincidence element 8, the first input of which is connected to the direct output of the first trigger 2, the reset input of which is connected to the output of the pulse counter 1, the output of the first "bit of which is connected to the first input of the first coincidence element 6, the second input of which is connected with the input bus 13, with a clock input, the third Chrygger 4, with the second input 40 of the element ITSH-HE 10 and with the start input of the first trigger 2, the output with the start input of the second trigger 3, the inverse output of which is connected to the reset input of the fourth trigger 5, 45 seconds the second input of the coincidence element 7, the output of which is connected to the second input of the third coincidence element 8, the second input with the inverse output of the third trigger 4, the information input and the reset input of which are connected to the output of the fourth coincidence element 9, the first input of which through the delay element 11 is connected to the control bus 14 and to the 55 clock input of the fourth trigger 5, the direct output of which is connected to the second input of the fourth match element 9, the information input to

/ 2

bus logical lines. The first 6 and fourth 9 match elements are AND elements, the second 7 and third 8 match elements are AND-NOT elements.

The device works in the following way.

The initial state of the triggers 3 - 5 is zero, and the trigger 2 is single. With inverted trigger outputs

The 3 and 4 unit levels go to the first and second inputs of the element 7, respectively. The zero level from the output of the element 7 goes to the second input of the element 8, from the output of which the unit level resets the counter

1 and prohibits the passage of clock pulses through element 10 to the clock input of counter 1. I

The leading edge of the synchronized pulse arriving at the bus 14 sets the trigger 5 to one state. At the same time, the synchronized pulse is fed to the input of the element 11, which is necessary to compensate for the switching time of the trigger 5 in the unit state. If the delay time of the synchronized pulse in the element 11 is equal to the switching time of the trigger 5 in the single state, then the unit level simultaneously arrives at both inputs of the element 9, the unit level from the output of which removes the zeroing from the trigger

4i prepares it for work. The first clock pulse arriving after this from the I3 bus by the leading edge sets trigger 4 to one state. The zero level from the inverted output of the trigger 4 sets the output of the element 7 to a unit level, which goes to the first input of the element 8. Since the trigger 2 is in the initial one state, then the first input of the element 8 has a single level. As a result, the zero level from the output of the element 8 removes the reset of the counter 1, translates the trigger 3 of. the zeroing mode is in storage mode and permits the passage of clock pulses through element 10 to the clock input of counter 1. But since the second input of element S1I-NOT does have a clock L pulse, then the output of element 10 remains at zero level. The falling edge of the first clock pulse, the passage through

element 10 is inverted and fed to the clock input of counter 1. As a result, a unit level is established at the output of the first bit of counter 1 and at the first input of element 6. The second clock pulse sets trigger 3 to one. From this point on, the suppression interval of the synchronized pulses begins.

By a level difference from zero to one at a single output of trigger 3, the single vibrator 12 forms at its output a pulse of a certain duration and polarity, which goes to the output bus 15. The zero level from the inverse output of trigger 3 flushes trigger 5, which in turn through the element 9 zeroes the trigger 4. However, the level at the output of the element 7 remains still single, since from the inverse output of the trigger 3 to the second input of the element, 7 enters the zero level. Therefore, further counting is permitted by the counter 1 of the inverted element of the 10 clock pulses. When the counting input of the counter 1 goes to pulses, a single level is set at its output and at the reset input of trigger 2. Since the zero input acts at the direct input of the flip-flop .2 at this moment, flip-flop 2 switches to the zero state. The zero level from the direct output of the trigger 2 sets at the output of the element 8 a unitary level, which is zeroed by the counter. 1 trigger 3. Resetting trigger 3 causes the reset of reset trigger 5 and, therefore, the suppression of synchronized pulses is eliminated. Resetting the counter 1 causes the trigger 2 to be placed in the storage mode. Upon the arrival of the (K + 1) -th clock pulse, trigger 2 goes to a single state, and the entire device returns to its original state.

If the front of the next synchronized pulse appears on the bus of the synchronized pulses before the moment of filling of the counter 1, this pulse is passed, as it cannot translate the trigger 5 into one state. Thus, synchronized pulses with a duration longer than the interval for suppressing the synchronized pulses can only lead to a one-time rotation of the device, and pulses that start in the interval of suppression of the synchronized pulses, and the ending 2 after this interval are completely suppressed. A condition is imposed on the output frequency.

f in “T. Bwv k

iO where K is the conversion factor of the counter 1; tskhkt frequency of clock pulses

on bus 13. If the short-time interference, the stroke through element 11 and element 9 to the information and zero inputs of trigger 4, begins before the moment on the first clock pulse, and ends before the start of the next clock pulse for the time required for zeroing trigger 4 and zeroing (via elements 7 and 8) of counter 1, then the following happens. On the leading edge of the first clock pulse, trigger 4 is switched to one state. From the moment of the end of the short-term interference, asynchronous resetting of the trigger 4 (via elements 7 and 8) of the counter 1 occurs. By the time the next clock pulse appears, the device returns to its original state after and (by triggering the trigger 5, which skips 5 The initial one state of trigger 5 does not affect the operation of the device, since the purpose of this trigger is to highlight the front

0 of the synchronized pulse after the end of the interval of suppression of the synchronized pulses. If, after exposure to a short-term interference, trigger 5 remains in unit state, then the synchronized pulse, passage through element 11 and element 9 to trigger 4, has the same effect if trigger 5 would switch by synchronized pulse

0 from the initial zero state to one. As a result, the immunity of the device with respect to short-term interference is ensured.

five

Claims (1)

Invention Formula A synchronization device containing a pulse counter, the output of which is connected to the reset input of the first trigger, and the first discharge output — to the first input of the first match element, the output of which is connected to the trigger start input of the second trigger, whose inverse output is connected to the first input of the second coincidence element , the third trigger, the third coincidence element, the output bus, the clock pulse bus, and the control bus are characterized in that, in order to increase the noise immunity, a delay element is introduced into it, the fourth element with a drop, an OR-NOT element, the fourth trigger, the third and fourth triggers are D-type, and a Single Vibrator, the output of which is connected to the output bus, the input is connected to the output of the second trigger, the reset input of which is connected to the reset input of the pulse counter , with the output of the third match element and with the first input of the R1PI-NOT element, the output of which is connected to the clock input of the pulse counter, the second input to the input bus, the second input of the first match element, the clock input of the third trigger and the start input of the first trigger, direct the output of which is connected to the first input of the third match element / the second input of which is connected to the output of the second match element, the second input of which is connected to the inverse output of the third trigger, the information input and the reset input of which are connected to the output of the fourth match element, the first input of which is connected through delay elements with the control bus and with the clock input of the fourth trigger, the direct output of which is connected to the second input of the fourth match element, the information input with the bus is logical units, the reset input - with the inverse output of the second trigger.