SU1374418A1 - Pulse delay device - Google Patents

Abstract

The invention can be used in devices measuring and computing. The delay device contains the shift register 1 on the triggers 2, ... 2, elements AND-NOT 3, ... 3, element OR-NOT 4. Introduction of element OR 5, element BAN 6, trigger control 7, generator 8 clock pulses , the front shaper 9 and the formation of new functional connections simplifies the device when the pulse is delayed by a time longer than its duration. 1 il.

Description

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The invention relates to a pulse technique and can be used in measuring and computing devices.

The purpose of the invention is to simplify the device when the pulse is delayed by a time longer than its duration. In the drawing there is a functional diagram of the proposed device.

 The device for delaying pulses contains shift register 1 on triggers 2 ... 2, AND-NOT elements 3., ... 3, element OR-EE 4, element OR 5, Prohibition element 6, control trigger 7, generator 8 clock pulses shaper 9 front.

Direct and inverse outputs of flip-flops 2 ... 2 shift register 1 through the corresponding elements AND-NOT 3,. . . 3 are connected to the inputs of the OR-NOT 4 element, the output of which is connected to the information input of the BAN 6 element, the output of which is connected to the first input of the OR 5 element, the output of which is connected to the counting inputs of the trigger 2, .. 2 register of the shift 1. Inverse output of the trigger 2 f shift register 1 is connected to a single control trigger input 7, the forward output of which is connected to the control input of the BAN 6 element and the control input of the generator clock 8, the output of which is connected to the second input of the OR element 5, the third input from is united with the output of the front 9 imager, the input of which is connected to the direct output of trigger 2. and zero input trigger 7 control.

The device works as follows.

In the initial state, in the absence of pulses at the input, triggers 2,. . .2 1 shift register 1 and trigger 7 are reset, at the outputs of the elements PI-H 3 ... 3 there are single potentials. At the output of the element OR NOT 4 there is a zero level, the element BAN 6 is open to zero potential from the direct output of control trigger 7. The same potential prohibits the operation of the generator 8 clock pulses. From the output of the element OR 5, the zero potential is present at the counting inputs of the flip-flops 2, ... 2 shift register 1.

A rectangular impulse arriving at a random moment of time at the input of the device arrives at the single input of trigger 2 of shift register 1 and by the front switches it to one state.

At the moment of switching the trigger 2- (where, 2, ..., n) of the shift register, which is possible only if there are potentials of the same name at the inverse output and a single input, as well as zero potential at the counting input of this trigger, the output of the NAND element 3 j, a pulse is formed from the potential drop at the outputs of trigger 2. shift register 1. The pulse thus generated is supplied through the OR-HЕ 4 element, open the BAN 6 element and the OR 5 element at the counting inputs of the register triggers. Thus, the front of the input square pulse moves along shift register 1. By dropping the square pulse, the register triggers successively switch to the zero (initial) state. After a time equal to the duration of the maximum impulse that can enter the device for the delay, the front of the rectangular impulse trigger 2 switches to one state. The value 1 is determined from the formula

  P.Myx

  Where

.- maximum

the duration of the input pulses; The trigger time. In this case, the potential drop at the inverse output of the 2p register of the register (from 1 to O) translates the trigger 7 of the control into one state. A single potential from the direct output of the control trigger 7 closes the prohibition element 6 and allows the generator to operate 8 clock pulses, the pulses of which through the OR 5 element arrive at the counting inputs of the trigger 2 ... 2 shift register 1. Now the pulse moves through the register with the generator frequency is 8 clock pulses, which can be chosen much less than the threshold frequency of operation of the logic elements with which it moved — a pulse up to this point in time. By varying the frequency of the 8 clock pulse generator, the device delay time is adjusted. With the appearance of a single potential at the direct output

de flip-flop 2, shift register 1 at the output of the front-side imager 9 a pulse is generated, which through the OR element 5 enters the counting inputs of the register flip-flops. At the same time, trigger control 7 is zeroed. In this case, the element 3AIIPEX 6 is opened and the generator 8 of clock pulses stops its operation. Then, the pulses formed as described above, from the output of the OR-NOT 4 element through the open element BAN 6, the OR 5 element goes to the counting inputs of the register triggers, and a delayed pulse appears at the device output, the duration of which will be exactly restored.

Claims (1)

Invention Formula A device for delaying pulses containing a shift register, a group of AND-NES elements, an OR-NOT element, moreover, the outputs of the triggers of the shift register are bit-wise connected through the corresponding AND-NOT element to the inputs of the OR-NOT element, a single input of the first and Q 5 0 five 184 The direct output of the nth trigger of the shift register is the input and output of the device, respectively, characterized in that, in order to simplify the device with a pulse delay for a time exceeding its duration, the OR element, the BANE element, the control trigger, the clock pulse generator, and the front driver, the output of which is connected to the third input of the OR element connected by the output to the counting inputs of the shift register triggers, the inverse input of the 1st trigger register of the shift register is connected to the single control trigger input, my output is connected to the control input of the clock generator and to the control input of the BAN, the output of which is connected to the first input of the OR element, and the information input to the output of the OR-NOT element, direct output of the (n-1) -th register trigger The shift is connected to the zero input of the control trigger and the input of the front driver, the output of the clock pulse generator is connected to the second input of the OR element.