RU1780186C - Pulse shaper with adjustable repetition frequency - Google Patents

Abstract

The invention relates to radio engineering and pulse technology, and can be used in frequency converting units of time equipment and reference frequencies, measuring instruments, synchronizers, as well as in receiving and transmitting devices of radio engineering systems. The device contains a reference oscillator 1, D (and elements 2 and 3, a frequency divider 4 with a nep'S-changeable division coefficient, counting trigger 6, RS-trigger 7. summing counter - counter 9, block 11 code comparison, subtracting counter 12. The listed blocks are connected as follows: 1-3-9-7-2- 12-11-6-4, 1-2, 1-4, 7-3, 4-6,4-7. by removing the limits on the variation of the division coefficient due to the parallel operation of the summing 9 and subtracting ^ 2 counters, the presence of new connections between the blocks. 2 il.

Description

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i / e.f The present invention relates to pulsed technology and can be used in frequency converting units of time equipment and reference frequencies, measuring instruments, synchronizers, as well as in receiving and transmitting devices of radio engineering systems. A device is known which comprises a variable divider frequency divider, a random number generator, a code comparison unit, a trigger, two AND elements and a frequency divider. The disadvantage of this device is the low phase stability of the output pulses, due to the non-optimal fractional conversion of the reference frequency, which leads to the formation of the output pulse sequence with maximum unevenness. The closest in technical essence is the device, which consists of a reference oscillator, a frequency divider with a variable division coefficient, three counters (addition, subtraction and reverse), seven AND elements, two triggers, two OR elements and one inverter. The essence is to minimize the unevenness of the output pulse sequence by alternating the intervals of dividing the reference frequency of the file (n + 1) at which the optimality condition is satisfied; the deviation A t of the output pulse from the corresponding hypothetical one (with period T (n + -73), where T0 is the period of the reference frequency, n, c, / 3, respectively, the integer part, the numerator and the denominator of the fractional division coefficient. The disadvantage of the prototype. there is a restriction n (s) on the limits of the change in the integer part of the fractional division coefficient, which narrows the range of the pulse repetition rate and reduces the speed of the device. The aim of the invention is to expand the range of the pulse repetition rate and increase The device is provided with a pulse generator with an adjustable frequency of the trace, comprising a reference oscillator connected in series, a frequency divider with a variable division coefficient and a trigger, a RS trigger connected in series, a first AND element and a subtracting counter, a totalizing counter whose clock input is connected to the output of the second element And, while the output of the reference generator is connected to another input of the first element And and the first input of the second element And, and the code input of the task dividing coagulant frequency divider with a variable division ratio is a first code frequency control input of the pulse shaper with adjustable repetition frequency, the second frequency control input of a code which is a code signal input of the summing counter preset. The indicated goal is achieved by that. that a code comparison unit is introduced into the device, the first code input of which is connected to the code output of the subtracting counter, while the output of the summing counter is connected to the R-input of the RS-trigger, the output of which is connected to the other input of the second element And, and the output of the counting trigger is connected to the installation an input of a divider of honesty with a variable division coefficient, the output of which is connected to the S-input of the RS-flip-flop, the output of the comparison unit of the cds is connected to the information input of the trigger, the installation input of which is the installation input a pulse sequence generator with an adjustable pulse repetition rate, the output of which is the output of a frequency divider with a variable division coefficient, while the input of the code signal for presetting the subtracting counter and the other code input of the code comparison unit are the third and fourth code inputs for controlling the pulse sequence generator with an adjustable repetition rate, the implementation of the device is illustrated in figure 1, where I is the reference generator, 2,3 - respectively, the first and the second elements And, 4 - a frequency divider with a variable division coefficient, 5 - the first code input for controlling the frequency of the device, 6 - counting trigger, 7 - RS-trigger, 8 - output of the device, 9 - summing counter, 10 - second code input for frequency control devices, I1 is a code comparison unit.

division code. At low and high potentials at its installation input, it operates with a conversion factor of n and (n + 1), respectively. The counting trigger 6 is implemented on the basis of clocked JK or D triggers, in which the information inputs are respectively J or D inputs. Using the third input (initial setting) in it allows you to set the desired

device operation mode (or

a) depending on its source

condition. In the first case, it is set to the single state, in the second case to the zero state. Trigger 7 is a conventional asynchronous RS flip-flop. Summing counter 9 is also a counter with a preset division code. It serves to count a or (y9-a) pulses of the input frequency in the modes respectively with or (2. If

counterE has a capacity of / 3, then a conversion factor equal to a is realized by applying to its input a code signal for presetting an additional code (inventor + dvd in the lower order) of the numerator of the fractional part of the division coefficient. The conversion factor (/ 9-a) is realized when a pre-setting code signal is supplied to its input for the direct code of the numerator of the fractional part of the division coefficient, since its capacity in this case becomes equal to () 8-a). The indicated operating modes of the counter 9 are known and detailed. No explanation is required. The subtracting counter 12 serves to form the difference (3) or (4). It is a reversible counter with a preset denominator code operating in the mode of subtracting the contents per unit upon arrival of the reference pulse. The number is written to counter 12 by the zeroing signal from the reverse transfer output (pin 13 of the 155IE6 chip) to its write enable input (pin 11 of the 155IE6 chip). This connection is internal, therefore, it is not shown in Fig. 1.

The code comparison unit 11 serves to check conditions (3) or (4). According to these conditions, code a or (/ 3-a) is supplied to its second code input in the respective modes. At

respectively cf or the fulfillment of conditions (3) or (4) at its output

high potential appears; otherwise, low potential.

By taking pictures of the device in

but from the initial state in which:

in the controlled frequency divider 4, counters 9 and 12 and the code comparison unit 11, the installation codes are entered respectively from the control inputs 5, 10, 13 and 14 of the device;

triggers 6 and 7 are in the single and zero states, respectively.

After the device is started, the input pulses (Fig.2a) of the heating generator 1 are received at the clock input of the controlled frequency divider 4 (high potential at the installation input of the frequency divider 4 (Fig.2b) forces it to operate with a coefficient (n + 1) (Fig.2c) ) The first output pulse of the device, the trigger 6 is reset, and the trigger 7 is set to a single state (Fig. 26, d) and allows the passage of the reference pulses to the inputs of the counters 9 and 12 (Fig. 2e). In this case, the contents of the counter 12 with each input pulse are reduced by one. After receipt of pulses on the counter 9a, it overflows and, with its output pulse, resets trigger 7 to the zero state (Fig. 2d, e), prohibiting passage

pulses to the inputs of the counters 9 and 12. In the counter 12 is recorded the content equal to (/ 3 - a) which is compared in block 11c a. If (/ 3-a) ci; then when the next pulse arrives at the output of the device, the conversion factor of the frequency divider 4 will not change and the processes in the device are repeated. The repetition of the cycles of formation of the output pulses with the interval pTo (Fig.2c) will occur

until the contents of counter 12 are less than a. In this case, the appearance of a high potential at the output of block 11 (Fig.2e) prepares trigger 6 for installation in a single state by the next

the output pulse of the device (figv, b). With the arrival of the next pulse to the output of the device in the frequency dividers 4, the division coefficient (n + 1) is set and the clock pulses arriving at the counter 12 read the remainder in it until it is completely zeroed. Then, with the signal for resetting the counter 12, which comes from the output, there is a reverse transfer to its write enable input, the code of the number j3 is entered into it.

Remaining from o: in the burst of clock pulses, the contents of counter 12 are read again. But now with the value / 3. The work of the frequency divider 4 with a conversion factor (n + 1) will be

12 is a subtracting counter,

13.14, respectively, the third and fourth code inputs of the control device;

15 - installation bypass device.

In Fig. 2, the processes in the device are illustrated by timing diagrams;

2a - at the output of the reference generator 1,

26 - at the output of trigger 6,

2a - at the output of 8 devices,

2g - at the output of the RS-trigger 7,

2d - at the clock inputs of the summing and subtracting counters 9, 12,

2e - at the output of the code comparison unit 11,

2g - at the output 8 of the device that implements a fractional division coefficient equal to n + -o 3 -x-p.

In Fig. 1, the reference oscillator 1 is connected to the second and first inputs of elements And 2, 3, respectively, and to the clock input of a frequency divider 4 with a variable division coefficient, in which the code input for setting the division coefficient is the first code input 5 for controlling the frequency of the device, setting input connected to the output of the counting trigger 6, and the output combined with the counting input of the trigger 6 and the S-input of the RS-trigger 7 is connected to the output 8 of the device. The clock input of the totalizing counter 9 is connected to the output of the second element And 3, the input of the preset code signal is the second code input 10 for controlling the frequency of the device, and the output is connected to the R-input of the RS-flip-flop 7, the output of which is connected to the first and second inputs, respectively elements And 2, 3. The first code input of the code comparison unit 11 is connected to the code output of the subtracting counter 12, in which the clock input is connected to the output of the first element And 2, and the input of the preset code signal is the third device control code input 13. The other code input of the code comparison unit 11 is the fourth control code input 14. device, the installation input 15 of which is the installation input of the counting trigger b, the information input of which is connected to the output of the code comparison unit 11.

By analogy with the prototype, we consider the algorithm of the claimed device.

In the general case, if at the output of a frequency divider with a variable division coefficient there were pulses, of which X were obtained by dividing the reference frequency by n and y by (n + 1), then the deviation of the v-ro pulse from the corresponding hypothetical

L (n + 1) To

(2)

In the specific case, if the violation of the optimality condition (1) occurs when

coefficient n (in mode a) for the kth

by the number of the output pulse, so that this does not happen, the k-th pulse is obtained at a coefficient (n + 1) in this case, the deviation of the k-th pulse from the corresponding hypothetical one as follows from (2) for and

equals

(k-1) n-Kn + 1)

The optimality condition (1) requires the inequality

(/ g-ka) That

i

from which (without taking into account the deviation sign Atk) the condition for switching the frequency divider with a variable division coefficient from coefficient n to (n-t-l) follows

/ 3-ka |.

Similarly, the condition / 5 - k (/ 5 - a) 4- is found for switching the frequency divider with a variable division factor from the coefficient (n + 1) to n. Since in the “max n and in the

and fi

 (/ 5 - ct) max - o-. THEN more strict inequalities will satisfy the switching conditions.

45

/ 3 - k a a in mode a t (3)

/ 3-k (-a) y5-a mode a

fifty

(

Formulas (3) and (4) determine the operation algorithm of the claimed device. The reference oscillator 1 is used to receive pulses of the reference frequency fo

 t; -. 4 frequency divider with variable

I about

dividing factor is a preset counter

only one cycle continues, since the contents of counter 12 at the end of this cycle (after subtracting the number a.) octanets are greater than a. Even in the worst case, when the remainder in it at the beginning of the division cycle by

(n + 1) is 1, and max 2. its contents at the end of this cycle / 5 - (and max - 1) will exceed t and, consequently, ctmax. Failure to fulfill condition (3) causes the appearance at the output of block 11 of low potential (Fig.2e), which prepares trigger 6 for resetting to zero state by the next output pulse (Fig. 2b) and switching of the frequency divider 4 from the coefficient (n + 1) to n. As a result, the device returns to its initial state from which all the described processes are repeated.

Operation of the device from ё

different from the first (

 only in the initial state; in which:

a direct code of the number a is entered into the counter 10 from the control input 10;

a code number (/ 3-a) is supplied to the second code input of block 11 from control input 14;

trigger 6 is set to zero by setting input 15.

For a more complete understanding of the algorithm of operation of the device, Fig. 2g shows the output pulse sequence obtained from the input pulse sequence (Fig. 2a) with a factor of about 3

In this diagram, the numbers in

nor n +

the interval of pulses and above them respectively indicate the conversion factor and the contents of the counter 12, at which the given pulse. As can be seen from FIG. 2g, each switching of the frequency divider 4 from a factor of 3 to 4 is preceded by a fixation of such content in the counter 12, the value of which is always less than o. 3, i.e. condition (3) for the entire operation cycle is fulfilled.

Unlike the prototype, where sums are generated in the reversible counter

Sxy (x +) "-y (JS-G :), if"

or

Sxy (y + 1) (/ 3-a) -X a if a

by sequential a, and then (y8 - c;) pulses of the reference frequency, or vice versa, in the inventive device for re-counting (/ 3 - a) or a pulses are not produced in the corresponding modes. This made it possible to remove one p (S-a) from the two limitations of the prototype: p a, p (a).

In the prototype, the minimum value of Pn1n / 3, since the restriction n (/ 3-a) must also be satisfied for 1, i.e. n (/ 9-1). In this case, n should not be Mei-ibLue than in, since -1.

AT

In the claimed device Pt1n% -, so

how the restriction of a must be satisfied for "max -1, i.e. n -1 which

/

performed at n equals.

Thus, the gain in PTT, and therefore, in expanding the frequency range, will be 2 times.

In addition, reducing the minimum

a value of n in 2 times will lead to a corresponding increase in the upper limit of the output frequencies and, consequently, to increase the speed of the device

also 2 times.

Claims (1)

In contrast to the prototype, which is implemented using a large number of elementary logic cells, the inventive device is implemented on large typical computer nodes with a high level of integration (the use of elementary logic cells is minimized: 2 versus 10 in the prototype). This makes it possible to further increase the reliability of the device as a whole, as well as to improve the overall dimensions of the objects in which the device is used. SUMMARY OF THE INVENTION Pulse generator with adjustable pulse repetition rate, comprising in series a reference oscillator, a frequency divider with a variable, a deletion coefficient and a trigger connected in series with an RS-trigger, the first element And and subtracting counter. A totalizing counter whose clock input is connected to the output of the second element And, G1, while the output of the reference generator is connected to another input of the second element And and the first input of the second element And, and the code input of the tasks of the division factor of the frequency divider with a variable division coefficient is the first pulse-frequency control input to the pulse generator with an adjustable repetition rate, and the second control input is the pulse whose frequency is the input of the preliminary signal installation of a totalizing counter, characterized in that, in order to expand the range of the pulse repetition rate and increase speed, a code comparison unit is introduced, the first code input of which is connected to the code output of the subtractive counter, while the output of the totalizing counter is connected to the R-BXO of the RS flip-flop whose output is connected to another input of the second element And, and the output of the counting trigger is connected to the installation input of the frequency divider with a variable division factor, you ||| "J3-cC -") Go i Go Go 13 10 7 i r ff 8 52 UlJiJUH UUIJfJH Fig. G the stroke of which is connected to the S-input of the RS-flip-flop, the output of the code comparison unit is connected to the information input of the flip-flop, the installation input of which is the input of the pulse shaper with an adjustable pulse repetition rate, the output of which is the output of the frequency divider with a variable division factor, while the input of the code signal for the presetting of the subtracting counter and the other code input of the code comparison unit are the third and fourth code inputs of the control pulse train sequencer with adjustable repetition rate. 1 f i ° i J3- / fc oC Го fjTo) ra f5 f2 9 8 J fff / J -; т4 | J | JiJ | JiJi