SU1495774A1 - Device for production of time intervals - Google Patents

Abstract

The invention relates to computing and automation and is intended to form accurate time intervals of a wide range that can be used in computer timers, as well as in master software devices of automation systems. The purpose of the invention is to expand the functionality by providing alternating cycles with a variable period. This is achieved by introducing a third register 9, a third comparison block 7, a trigger 10, 11, and their connections. The proposed device allows to obtain time intervals of increased accuracy due to the fact that, in addition to the main stage of the device, producing pulses with a follow-up period determined by the first constant, a correction stage is introduced, which increases the period of impulses following a certain time interval, resulting in the accuracy of the total time interval increases. 2 Il.

Description

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3. 1495774

variable period. This is achieved by introducing the third register 9, the third I block 7 comparison, the triggers 10, 11, and their connections. The proposed device allows to obtain time intervals of increased accuracy due to the fact that, in addition to the main stage of the device, the invention relates to computing and automation and is intended to form exact time intervals of a wide range that can be used in timers drop-down machines, as well as in defining software devices of automation systems.

The purpose of the invention is to enhance the functionality by providing alternating cycles with a variable period.

FIG. 1 shows a block diagram of the device; in fig. 2 - macrocycle device operation ..

The device contains an AND 1 element, a counter 2, a comparison block 3, a register 4, a counter 5, a comparison block 6 and 7, a register 8 and 9, triggers 10 and 11, an AND 12 element, an OR 13 element, a HE element 14, a clock input 15 , the input 16 of the recording resolution, the input 17 of the initial installation and the output of the IS

The device works as follows.

In the initial state, the counters 2 and 5 are zeroed; at the outputs of blocks 3, 6 and 7, the comparison potentials are zero,. triggers 10 and 11 in the zero state

The clock pulses are passed through the element I 1 to the input of the counter 2 "All counters of the device are built on 1, K-triggers, i.e. change their connection on the falling edge of the incoming pulses.

The value of the desired variable interval (the required number of accumulated pulses) is stored in register 4.

When the content of counter 2 and register 4 coincides, a high potential is generated at the output of comparison unit 3, which blocks the further arrival of fixed frequency pulses at the input of counter 2

A pulse with a period determined by the first constant is inserted into the corrective cascade, which increases the pulse duration over a certain time interval, resulting in an increase in the accuracy of the total time interval of 2 or more.

The passage of the signal from the output of the comparison unit 3 through the element And 12 controls the I, K-trigger 10.

The state of the trigger 10 when a positive signal appears at the output of the comparison unit 3 is determined by the state of the trigger I.

The zero potential at the single output of this trigger, which enters the 1 input of the trigger 10, maintains the latter in the zero state, regardless of the value of the signal at the output of the comparison unit 3.

The signal that passed through AND 12 enters the input of counter 5 and, through the OR element 13, returns the counter 2 to the initial state.

As a result of the reset of the counter 2, a high potential disappears at the output of the comparison unit 3 and the element NOT 14 is released through the element 14 and the element I 1 and the receipt of fixed frequency pulses at the input of the counter 2 is released

The main cascade of the device starts a new cycle of operation before comparing the contents of counter 2 with the value of register 4. At the same time, at the output of the And. 12 element, pulses appear with a period determined by the first constant.

The period is equal to

(const 1 + 1) T

about

(one)

where Tp is the period of following pulses of a fixed frequency. The average accuracy of the period of the following pulses is 0.5 of the period of the pulses of a fixed frequency.

The device operates as follows, until a high potential is reached at the output of the comparison unit 6, indicating a match 5

Research Institute of the contents of the counter 5 with the second constant. In this case, the trigger 11 is switched to the single state. The next clock pulse switches to the single state and the trigger 10, as a result of which, at the next occurrence of a high potential at the output of the comparison unit 3, the pulse from the generator does not pass through the AND 12 element. the potential at the output of the comparison unit 3, the pulse switches the trigger 10 to the zero state and opens the element AND 12 for passing the next pulse from the generator. As a result, the counter 2 is reset and the high otentsial at the output of comparator 3, the trigger 10 again ustanovits 1 and closes the AND gate 12. The flip-flop 10 is switched to ON again in the next cycle and otkrshaet

element and 12. 1

So, as long as

trigger 11 is in a single state; the duration of the time intervals between pulses at the output of the element 12 is longer for one period of the pulse generator

T (const 1 +

2) T,

(2)

When the contents of the counter 5 coincide with the third constant, a high potential arises at the output of the comparator block 7, which resets the trigger 11, as a result of which the correction cascade is blocked, and the new macro cycle of the device operation begins

FIG. 1 conventionally depicts the macrocycle of the device,

T, 1 const 2 + Tj Cconst 3 - const 2)

The choice of constants. To determine the constants, the pulse interval of the main cascade T must be specified, which can be obtained with an average accuracy of 0.5 period of the master oscillator, and also the duration of the device macrocycle must be specified, in which the error must be corrected.

In the general case, T,, T T, the first constant is defined with reference to (1), as a whole part of the ratio

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T - Ta

tg

The remainder D from the division is the negative error in the formation of the period T; U T - T,.

L Attitude - determines how ka

about

the part of the macrodisk should be formed by pulses with an extended follow-up period (T) to correct for the error to the second and the third constant is determined from the ratio

const 2 const 3

  v T, T /

const 2 bb. f, 1 J-o

25

thirty

40

Claims (1)

; Formulaisobre shadow A device for forming time intervals containing two elements AND, element NOT, two counters, two comparison units, element OR, two registers, the first inputs of the first and second elements AND connected to the clock input of the device, the first input of the SHS element is input the initial installation of the device, the output of the first element And connected with the counting input of the first 35, the reset input of O which is connected to the output of the OR element, the group of bit outputs of the first counter is connected to the first group of information inputs of the first comparison unit, the second group of information inputs of which is connected to the group of bit outputs of the first register, the write resolution of the first and second records the registers are connected to the enable entry of a device, the group of information inputs of the first register is a group of inputs of the period of the first interval of the device, the group of information 5Q second register rows into- L is a group of inputs specifying interval period of the second device, comparing the first output equality unit connected to the input of NOT circuit, 55 the output of which is connected to the second input of the first element I, the group of discharge outputs of the second counter is connected to the first group of information inputs of the second comparison unit, the second group of information inputs of which are connected to the group: the bit outputs of the second register, characterized in that expanding functionality by providing alternating cycles with the pregnant period in the & g: the first and second triggers, the third comparison block and the Third register are entered, the group of bit outputs of the second counter is connected to the first group of information inputs of the third block of comparison, the second group of information inputs of which is connected to the group of bit outputs of the third register The write enable input of which is connected to the device write enable input, group. information inputs. The third register is a group of device cycle input inputs, the equality output of the second comparison unit is connected to the 1 input of the first trigger, the K input of which is connected to the output of the third comparison unit, the synchronous inputs of the first and second triggers are connected to the clock input of the device, the equality of the first comparison block is connected to the second input of the second element, with the K-input of the second trigger, 1-input of which is connected to the direct output of the first trigger, the inverse output of the second trigger is connected to the third input of the second element I, the reset inputs in O of the first and second triggers are connected to the input of the initial installation of the device, the output of the second element AND is connected to the counting input of the second counter, with the second input of the element OR, and is the information output of the device Phage.