SU1418768A1 - Hybride integration device - Google Patents

Description

The invention relates to hybrid computing and can be used in analog-digital computing systems and automation devices for long-term integration of an analog signal.

The aim of the invention is to improve the accuracy of integration and reduce hardware costs.

Fig. 1 shows a functional: scheme of the proposed device; in: FIG. 2 - voltage plots that explain the principle of the device I; in fig. 3 - functional diagram i of the reference current generator; in FIG. 4 - shaper temp; Tervalov.

: Hybrid integrating device: in (fig. 1) contains the first 1 and second; a swarm of 2 integrators, the output of each of which is connected to the first input I of the first 3 and second 4, respectively; comparators, switch 5, the first and second outputs of which are connected to the inputs of the first 1 and second 2 integrators, respectively, a large-scale resistor 6, the first output of which is information input 7 of the device, the generator 8 reference currents, the first and second the outputs of which are connected to the inputs of the first 1 and second 2 integrators respectively, counter 9, third, first and second multiplexers 10-12, elements NOT 13 15, trigger 16, elements 17 and 18, shaper 19 time intervals; the clock input 20 of the device, and the outputs of the elements And 17 and 18 are information outputs 21 and 22 of the device I,

; The generator 8 reference currents (Fig. 3), contains switches 23 and 24, resistors 25 and 26, amplifier 27 DC, transistors 28 and 29.

Shaper 19 time intervals (Fig. 4) contains an integrating chain, performed on the diode 30, the resistor 31 and the capacitor 32, and the inverter 33,

The device works as follows.

In integrators 1 and 2, the dual integration mode is alternately implemented. The integration order is set using the logical variable b, representing the output of the highest (nth) digit of the counter

9. At b. and tj - t /, diagram f, fig, 1), Source of integrable

0 voltage at the same time through the scale resistor 6 and switch 5 is connected to the input of the first integrator 1, the first generator output 8 reference currents are de-energized, and the second is activated - the reference current of one direction or another flows in it (depending on the voltage sign at the output second 2 integrator), which produces a reduction in voltage (in absolute value) to zero at the output of the second integrator 2, Value 1)., which is the integral of the input voltage during the time of the first integrator, is converted at is a pulse duration tg - t. This time interval is filled with clock pulses, the number of which is proportional to the integral of the input

0 effects during the first integration. These pulses appear at the output 22 of the negative increment, since Uj 7 O, which is a sign of a negative integrable voltage. If Uj 0, then output pulses appear at the output 21 of the positive increment (time interval t5 t, diagram f, fig 2). If J) 1, the second integrator 1 implements the second integration (time intervals tj - tzi t, diagram d , fig, 2), and in the second integrator 2 - the first integration (time intervals t4 and t. t - tg, chart

 f, fig, 2), the source of the integrated voltage is through a large-scale resistor 6 and a switch 5 is connected to the input of the second integrator 2, the second output of the generator 8 reference

0 currents de-energized. The first output of the reference current generator is activated. The process of the second integration is identical to that described above, similar to the process in the second integrator; therefore, in the time interval t - tj, there appear impulses of negative increment of the input voltage integral, and in the time interval tj - t

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positive increments of the input voltage integral. Analysis of the principle of the device shows that the first 1 and second 2

integrators alternately integrate the input action, which contributes to the continuous integration of the input signal, and convert the increments of the integral of the input voltage in the sequence I1 of the pulses, the numbers and sign of which (output number) correspond to the magnitude of the increment of the integral and the sign of this increment. To implement the described algorithm of the device operation, a control generator 8 reference currents is necessary (Fig. 3). When g O switch 23 is in the upper position, and a reference current of positive polarity is formed at the generator output 8 of the reference currents (Fig. 3, this direction is indicated by the arrow). When g switch 23 is in the lower position and a negative polarity reference current is formed at the output of the generator. The reference current branch to the corresponding integrator is carried out by the switch 24, with the generator 8 having reference output connected to the second integrator 2, the first generator output is open, and the generator 8 reference currents being activated output to the first integrator 1, the second generator output open At b o, this allows the reference current of the corresponding sign to be directed to the first integrator 1. In this case, until t (t,) (diagram f, fig. 2), there is a decrease (in absolute value) to zero potential of the output voltage of the second integrator 2. After the second integration mode, the second integrator 2 is transferred to the stabilization mode of the initial point of the input potential, which consists in forcibly keeping it near the zero potential level. This mode is implemented by applying to the integrator input a reference current opposite in sign to the output voltage of this integrator. In this case, at the output of the second integrator 2, an alternating voltage is observed (with a constant component near the level of zero potential), the amplitude and frequency of which

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depends on the constant integration time of the integrator, the sensitivity of the comparator and the propagation delay time in the reference current direction switching control circuit. At this time, in the first integrator 1, the first integration of the input voltage is performed.

When b 1 in the second integrator 2, the stabilization mode stops and it goes to the first integration of the input voltage (the input of the second integrator 2 is turned off by the switch 24 from the generator 8 of reference currents and connected to the information input of the device by the switch 5). First integrator 1 is first in the second integration mode (moments t to. T, - tg, diagram d, Fig. .2),

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Counter 9, multiplexers 10-12, elements NOT 13-15, trigger 16, elements AND 17 and 18, shaper 19 time slots are designed to form three integrator modes of operation: the first and second integration and the stabilization mode of the reference point and the time interval filled clock pulses whose number and output number determine the sign and integral of the input voltage.

The operation of comparators 3 and 4 can be described by the following equation:

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The timing diagrams of the first 3 and second 4 comparators (n and g, respectively, fig. 3) explain the principle of their operation.

Multiplexer 10 and trigger 16 are designed to fix the sign of the integrable voltage.

When b 0, the first integration occurs in the first integrator 1. The first comparator 3 selects a significant part of the output signal, which is transmitted through the multiplexer 10 to the information input of the trigger 16.

The principle of operation of multiplexers is as follows: in the case.

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when at the control input X O, the I signal supplied to the first information input is connected to the output of the multiplexer, when X 1, the output signal fed to the second information input is connected to the output. The voltage corresponding to the sign of the input and integrating voltage is fixed in the trigger 16 by a clock pulse coming from the transfer output of the counter 9 at the end of each cycle of the first integration. At b 1, the sign of the integrator in the second integrator 2 is fixed. The output signal of the trigger 16 determines the output number, at which clocks appear. With a negative integrable input voltage (t 0), the passage of clock pulses to the second output 22 of the device is allowed, and with a positive (t 1) - to the first output 21.

Multiplexers 11 and 12, elements NOT 14 and 15, shaper 19 time slots are designed to form a time interval, the duration of which is proportional to the input voltage integral. Multiplexer 11 transmits to its output signals corresponding to the second integration mode (the duration of which corresponds to the input voltage integral) and the stabilization mode of the initial point in turn between the first 1 and second 2 integrators.

The HE element 14 and the multiplexer 12 form a signal in which the time interval corresponding to the second integration in the integrators always takes the value n O (moments tg - t, t - tj, ts - tf, t.g, diagram n, Fig. 2). When a negative input voltage is integrated, such a signal is formed naturally and transmitted to the output of the third multiplexer 12. In the case of a positive integrating voltage, the signal g is inverted and transmitted through the second information input of the third multiplexer 12 to the output. The control signal, taking into account the sign of the integrable voltage, is removed from. trigger output 16.

The shaper 19 time slots is intended to form

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temporary gate, i.e. single resolution signals proportional to the integral of the input signal. The input signal n (diagram p, figure 2) consists of an information signal of zero potential and an interfering signal. The integrator chain of driver 19 forms a single signal from a high-frequency interfering signal. In the inverter code 33 (the element is NOT), a signal is received in which the information part has the potential of logical 1, and the interfering signal has the logic-

Thus, an information signal is generated, which is fed to elements AND 17 and 18 and determines the interval during which the output of the device is received

clock pulses Taking into account the sign of the integrable voltage.

The stabilization mode of the reference point is the rapid change in the integrable voltage, while

the output voltage of the integrators oscillates around the threshold of the comparator, equal to zero potential. The end of the second integrator: the vani is accompanied by the intersection of the output voltage of the integrators

2 and 3 through the level of zero potential. Comparators for this situation

3 and 4 react by changing their output. This signal change through multiplexer 11 is fed to the control input of switch 23 and changes the polarity of the reference voltage, which is fed to the input of that integrator in which the second integration is completed. Due to the change in the polarity of the input signal, the output voltage of this integrator will again begin to decrease (in absolute value) to zero potential and again cross

the comparator threshold, which will cause the polarity of the reference voltage to be switched again.

The advantage of the proposed device in comparison with the known one is to increase the accuracy characteristics of the integration obtained by eliminating the temperature and installation drift of the initial level of the first integration and reducing the hardware costs associated with changing the operating modes of a number of elements.

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Claims (1)

A HYBRID INTEGRATING DEVICE containing the first and second integrators, the outputs of which are connected to the first inputs of the first and second comparators, respectively, connected by the second inputs to the zero potential bus, a switch whose input is connected through the scale resistor to the input of the hybrid integrating device, and the first and second outputs are connected with the inputs of the first and second integrators, respectively, associated with the first. and the second outputs of the reference current generator, the counter, the input of which is the input of the clock pulses of the hybrid integrating device and connected to the first inputs of the first and second elements And, the outputs of which are the information outputs of the device, the output of the highest level of the counter is connected to the control input of the switch that switches the input of the reference generator currents and through the first element NOT to the control input of the first multiplexer, the first and second information inputs of which are connected to the outputs of the first and second comparators, respectively, and the output is connected to the first information input of the second multiplexer and through the second element NOT to the second information input of the second multiplexer, the control input of which is combined with the second input the first element AND and with the input of the third element NOT, the output of the third element is NOT connected to the second input of the second element AND, the third multiplexer and trigger, in that, with tse- _β pour 1S improve the accuracy of integration and reduction of apparatus cost, a generator device introduced slots, whose input is connected to the output of the second multiplexer, and an output connected to a third input of the first and third input of second AND gates, the output MSB the counter is connected to the control input of the third multiplexer, the first and second information inputs of which are connected to the outputs of the first and second comparators, and the output is connected to the information input of the trigger, the sync input of which connected to the counter transfer output, and the output connected to the control input of the second multiplexer, the output of the first multiplexer connected to the pressure input by the polarity of the reference current generator. S „„ 1418768