SU1261095A1 - Pulse repetition frequency multiplier - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in automation and measuring devices. The purpose of the invention is to increase reliability. For this, a device containing a pulse generator 1, a frequency divider 2, buses: input 5, output 3, D-flip-flop 4, new connections are introduced. The frequency of the pulses at the output of generator 1 should ensure the completion of the cycle of operation of the multiplier of the pulse frequency before the arrival of the next input pulse. 1 il. Od SO Sp

Description

The invention relates to a pulsed technique and can be used in automation and measuring devices.

The purpose of the invention is more reliable. The drawing shows the electrical functional diagram of the proposed device4

The pulse frequency multiplier contains a pulse generator 1, the output of which is connected to the clock input of the frequency divider 2, the output of the first bit of which is connected to the output bus 3, the inverse output of the latter with the R input of the D flip-flop 4, the output of which is connected to the reset input of the divider 2 frequencies, D-input - with a bus of a logical unit, C-input - with an input bus 5,

The device works as follows, -. in a way.

In the initial state, at the output of D-flip-flop 4, there is a zero ypoBeHb which sets divider 2 to the zero state. In this situation, the output signal from its output does not affect the pa- rameter of divider 2. For etrm output, the generator 1 pulses are considered divisor 2 until the switch is triggered by S. Lisin. Order 5244/57

Compiled by A.Sokolov Tehred L.Oleinik

Corrector M

Circulation 816 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35., Raushsk nab. 4/5

Production and printing company, Uzhgorod, st. Project, 4

hera of the last bit. At this point, the inverse output of the last | the bit divider 2 appears the zero level, which sets the D-flip-flop 4 to zero, and the entire device. in - in the initial state.

Thus, at the output of the first bit, the splitter 2 after each

the input pulse appears the number of pulses proportional to the number of bits. The frequency of the pulses at the output of the generator 1 must ensure the completion of the cycle of the multiplier of the pulse frequency before the next input pulse.

Claims (1)

Invention Formula  A pulse frequency multiplier containing a gene; pulse ramp, D-flip-flop, the output of which is connected to the reset input of the frequency divider; the first bit of which is connected to the output bus, the inverse output of the last bit is connected to the R-input of the D-flip-flop, the D-input of which is connected to the bus of the logical unit), the C-input to the input bus. Proofreader M.Sharoshi