SU1188722A1 - Synchronizing signal generator - Google Patents

Abstract

SYNCHRONTIME FORMER, comprising a clock pulse generator, a query bus and a shift register, the outputs of which are connected to the first output buses and the first inputs of the AND block whose outputs are connected to the second output buses, characterized in that, in order to improve reliability and enhance functionality , the memory register is entered into it, the information inputs of which are connected to the outputs of the shift register, the reset input of which is connected to the query bus, the control input of the clock generator the pulses and the reset input of the memory register, the outputs of which are connected to the second inputs of the AND block and additional output buses, and the recording input of the memory register is connected to one of the outputs of the clock generator, the other output of which is connected to the shift register shift input. (L

Description

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The invention relates to a pulse technique and can be used in asynchronous and synchronous devices that perform the necessary operations with the help of clock signals.

The purpose of the invention is to increase reliability and expand functionality by simplifying the device and generating signals with a resolution equal to the half-period of the master clock generator, with the possibility of using the device in synchronous and asynchronous modes.

FIG. 1-3 shows the block diagram of the sync driver and timing diagrams.

The sync driver contains a shift register 1, an AND 2 block, a query bus 3, the first 4 and second 5 output buses, a 6 clock pulse generator, a memory register 7, and additional output tires 8.

The request bus 3 is connected to the control input of the generator 6 clock pulses, the reset inputs of the shift register 1 and memory register 7, the shift and write inputs of which are connected to the generator outputs 6 clock pulses, and the outputs of the shift register 1 and memory register 7 are connected respectively to the output tires 4 and 8, as well as with the inputs of the block of elements And 2, the outputs of which are connected to the output tires 5.

Example. The shift register 1 is made on eight D-flip-flops 9 and 10 with a common installation in the "O. The outputs 11 to 17 of the D-flip-flops of the shift register 1 are connected to the information inputs of the subsequent D-triggers. The outputs 12 and 17 of the shift register 1 are connected to the first inputs of the block of elements And 2. The outputs 11, 13, 14, 16 and 18 of the shift register 1 are connected to the output buses 4, and the outputs 12, 14-17 of the shift register 1 are connected to the information inputs of the register memory 7.

The block of elements And 2 contains the elements And 19, AND-NOT 20 and 21, And 22-24, the second inputs 25-33 of the block of elements And 2 are connected to the outputs of the memory register 7, and the outputs

34-39 unit blocks And 2 are connected to the output bus 5.

The clock pulse generator 6 contains the element AND-NOT 40, the first input of which is connected to the query bus 3, the element AND-NO 41, the inputs of which are connected to the output of the element AND-NOT 40, the element AND-NOT 42, the inputs of which are connected to the output of the element AND -NE 41, 1K-flip-flop 43, the S-input of which is connected to the query bar 3, the C-input is connected to the output of the AND-HE element 42, the inputs "I" and "K" are supplied with the level "1, and the outputs 1K-flip-flop 43 clock generator 6 and connected to the second (write and shift) inputs of memory register 7 and shift register I. Generator RC chain Section 6 consists of resistors 44 and 45 and a capacitor 46. Memory register 7 contains eight flip-flops 47 and 48, outputs 49-53 of which are connected to output spikes 8. Request bus 3 is connected to the reset inputs of the shift register 1 and memory register 7.

The sync driver works as follows.

After turning on the supply voltage in the absence of a positive control signal on the query bus 3, the shift register 1 and memory register 7 are zeroed, and the trigger 43 is set to S one at the S input. When a positive control signal appears on the query bus 3, the controlled master oscillator starts operating.

b clock pulses. Paraphase clock pulses from the output of the trigger 43, which is a frequency divider and designed to receive pulses of the generator with a duty cycle of two, are fed to the shift input of the shift register 1 (from the Q output of the trigger 43) and to the write input of the memory7 (from the Q output of the trigger 43). The first positive differential of a series of clock pulses enters information into the first trigger of the shift register 1. A high level from the output 17 of the first trigger of the shift register 1 is fed to the information inputs of the first trigger of the memory register 7 and the second trigger of the shift register 1. A half interval of the clock interval occurs the entry of single information into the first trigger of the register of memory 7 and after one period into the second trigger of the shift register 1. Thus, after half a period at the output of dvogo memory register trigger 7

and after one period, at the output of the second flip-flop of the shift register 1, positive voltage drops are generated. The next differences in the signals from the outputs of the generator 6 clock pulses are set to one state by the subsequent triggers of the shift register 1 and the memory register 7, as shown in FIG. 3. The presence of paraphase series formed by the trigger 43 allows information to be entered into the shift register 1 and memory register 7 with a time shift equal to the generator half-life 6. The clock pulses from the outputs of the shift register 1 and memory register 7 arrive respectively on the output wedges 4 and 8, as well as on the inputs of the block of elements I 2,

the outputs of which are the formation of signals of the required duration. The organization of the operation of the shift register 1 and the memory register 7 on paraphase series provides the possibility of generating control signals using an AND 2 block of units with a discreteness equal to the half-period of the master oscillator 6. After the formation of a series of clock signals, the master oscillator 6 continues.

But the formation of a new series takes place only after the request signal is removed (setting the shift register 1, memory register 7 and trigger 43 to the initial state) and the signal arrives on the request board 3.

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Claims (1)

SYNCHRONOUS SHAPER comprising a clock generator, a request bus and a shift register, the outputs of which are connected to the first output buses and the first inputs of the AND block, the outputs of which are connected to the second output buses, characterized in that, in order to increase reliability and extend the functional opportunities, a memory register is entered into it, the information inputs of which are connected to the outputs of the shift register, the reset input of which is connected to the request bus, the control input of the clock and a reset input memory register, whose outputs are connected to second inputs of the AND block and additional output lines, and the memory write register input connected to an output of the clock generator, the other output is connected to the input of the shift register shift. QO QO Yu yo Figure 1