SU1383505A1 - Converter of binary code to binary-coded decimal code of angular units - Google Patents

Abstract

The invention relates to the field of automation and digital computing and can be used in the construction of the following binary-decimal converters. The aim of the invention is to reduce the conversion time. The goal is achieved by the fact that the converter.

Description

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with | observatcii group of elements EXCLUDE- 11 | EE ШШ 1, adder 2., register.3, with | comparison of 4, elements AND 5.6, element OR 7, binary-decimal forward counter 9, additionally

a switch 14, a constant reference device 15, a sequential approximation register 16, a counter 17, a one-shot 18, an AND 19 element are introduced. 1 il.

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The invention relates to automatic and computer technology and can be used in automatic control systems, information gathering, ontrol of production processes for visual evaluation in constant angular and variable angles represented by in binary digital code.

The aim of the invention is to save time ready.

The drawing shows the block diagram of the proposed Converter.

The converter contains a group of 1 e} lementbv EXCLUSIVE OR, adder 2 p | register 3, circuit 4 comparison of codes, elements AND 5 and 6, element OR 7, element HE 8, binary-decimal reversive counter 9, input 10 conversion controller, input 11, reset of preamplifier, clock input 12 of transducer, information11; ionizer 13 input of transformer, switch 14, jToHHHoe storage device 15, register of 16 consecutive approximation, counter 17, one-oscillator 18, s-lemth and 19.

To achieve this goal, in g (the proposed converter uses a combined algorithm for obtaining the equivalent input code, which begins with successive approximation steps (bitwise, starting with the highest bit), and continues with the following mode of operation before comparing the codes in circuit 4 .

The Converter operates as follows.

The signal at the reset input .11, due to the power on or independently of this, is set-;; to the initial state, register 3,

as well as a binary-decimal reversible counter 9, the sequential approximation register 16 and counter 17. The first clock pulse from the input of 12 clock pulses passes through the AND 19 element, since its second input is connected to the inverted output of the counter 17, which is in a single state. From the output of the AND element 19, a clock pulse follows the clock input of the register 16 of successive approximation, the outputs of which are set to code 01,. . 1, (see table), corresponding to the first half of the full angle. This code as an address goes to the permanent storage device 15, where two groups of words are written: D - codes of which correspond to the binary-decimal code of the N size of the angular measure, E - codes of which correspond to the binary code of the N of the angular measure. The code D from the read-only memory through the switch 14 is fed to the input of register 3, from where it is transferred by a pulse from the output of the OR element 7 to the first input of the comparison circuit 4 and to the input of the adder 2. The output of the adder 2 is connected to the second input of the switch 14, which in the presence of a single level at the output of the counter 17, disconnects it from the input of the register 3.

The table shows the transitions of the register of the approximate approximation.

At the second output of the comparison circuit 4, a single signal is generated if the code at input 13 is greater than code D, and zero if the code at input 13 is less than code D. The comparison signal is written to the high-order register 16 of the sequential approximation as it arrives at its second clock input pulse (see tabltsu). On the second clock pulse from input 12, similarly to that described, a quadrant is determined, in which there is an angle equivalent to the ELECTRONIC code. In this case, in the register 16, two equalities of the D code are formed.

On the third, fourth, etc. pulses are determined by octant, sixteen, etc. the parts of the total angle in which the value of the definable angle is located. At the same time, at the outputs D and E of the permanent storage device 15, codes are stored that are stored at addresses corresponding to the specified full angle parts in binary and binary-decimal codes.

Virtually no need. in the number of bits determined by a sequential approximation larger than four, it is therefore advisable to control the transition to the next mode of operation using the third bit output of the Q counter 17. Upon arrival from the clock input of the 12 fifth clock pulse, the zero signal is generated at the output of the counter 17 and Element And 19 is closed. On the zero level at the output of the counter 17, the switch 14 disconnects from the input of the register 3 the output D of the permanent storage device 15 and connects the output of the adder 2 to the input of the register 3,

From the decay of the logic level at the output of the counter 17 by the one-sided 18, a pulse is generated that controls the recording of the binary-decimal code of the angular units E from the output of the permanent storage device 15 in a binary-to-nine reversible counter 9 on its information inputs.

Thus, the block diagram of the converter corresponds to that required for its operation in the following mode and, starting with the sixth clock pulse, the converter functions in full accordance with the description of its operation, given for the known device, but within 1/6 of the total angle. ;

The time required for the converter to enter the next mode in this case is 16 times less, respectively, than at the full angle.

Claims (1)

Invention Formula Binary code to binary decimal code converter five 0 five 0 five 0 five 0 five a block containing an adder, a pei-ister, a comparison circuit, the first and second elements AND, the element OR, a binary-decimal reversible counter, the element NOT and a group of elements EXCLUSIVE STI, the first inputs of the elements of the ULTR1 OR of the group are connected to the input of the constant constant, the second inputs connected to the output of the More comparison circuit and to the transfer input of the adder, the first inputs of which are connected to the outputs of the elements of the ULTIMATE OR group, the second, the inputs of the adder are connected to the outputs of the register and the first inputs of the comparison circuit, the second inputs to The second is connected to the information input of the converter, the reset input of which is connected to the reset inputs of the register and the binary-decimal reversible counter, the outputs of which are the outputs of the converter, the clock input B of which is connected to the first inputs of the first and second elements I, the second inputs of which are connected respectively to Smaller and More outputs of the comparison circuit, and the third inputs of the first and second elements AND are NOT connected to the reset input of the converter, the inputs of the first and second elements AND are connected respectively, with the increment and decrement inputs of the binary-decimal reversible counter and the first and second inputs of the first OR element, the output of which is connected to the register entry input, characterized in that, in order to reduce the conversion time A.i. This storage device, a single-oscillator, a counter, a third And element and a sequential approximation register, the clock input of which is connected to the output of the third And element and to the synchronous input of the counter, the output of which is connected to the first input And, with the control input of the switch and through the one-shot with the input of the record of the binary-decimal reversible counter, the information inputs of which are connected to the output group of the binary-decimal code of the persistent storage device whose output group of the binary code is connected to the first group of inputs of the switch , the second group of inputs of which is connected to the outputs of the adder, and the outputs of the switch are connected to information 5 13835056 register inputs, the address, the reset input of the register of post-runs of the permanent memory approximation is connected to The probes are connected to the outputs of the register input of the converter reset and successive approximation, where the counter is reset, the clock input the information input of which the transducer is connected to the second Not with the output of More circuits with the input of the third element I.