SU1126964A1 - Device for organizing queue - Google Patents

Abstract

A DEVICE FOR ORGANIZING A QUEUE, containing E (m groups of elements I (where n is the number of application sources), Eo P registers, an encoder and a decoder, the output group of which is a group of information outputs of the device, the inputs of the decoder are connected to the outputs of IRC-x bits of regis; grov, the control inputs of which are connected to the clock input of the device, the group of request inputs of the device are connected to the input group of the encoder, i - and (i g 1, ..., Pog n) whose output is connected to the first inputs of the AND elements i -and groups, the outputs of which are connected to information inputs of the 1st register, characterized in that, in order to reduce hardware costs, it contains L elements OR NOT and n-2 elements OR, and the i -th and inputj -th (j-1, ...,) l ) the element OR is NOT connected to the output of the jth digit of the jth register, the output of the jth element OR is NOT connected to the second inputs of the jth elements AND groups and to the () input of the elements OR from the first to ( | -1) th, the output of the j-ro element OR is connected to (Roo, n + 1) th input of the th element OR, the output of the first element OR NOT is connected to the first input of the second element OR NOT. S

Description

The invention relates to computing and can be used in numerical systems.

A device for servicing applications in the order of arrival is known, containing 5 groups of elements AND, registers, an encoder, a group of elements OR, a group of triggers and a decoder.

Disadvantages of the known device - About high hardware costs and low speed.

The closest to the proposed is a device for servicing applications in the order of arrival, containing groups of elements AND, registers, an encoder, two decoders, a counter

and the element OR G21. The disadvantage of this device is large hardware costs. 0

The purpose of the invention is to reduce the hardware cost of the device.

The goal is achieved by the fact that a device for queuing containing Bog and groups of elements I (where h is the number of sources of the application), Sod and registers, an encoder and a decoder, the output group of which is a group of information such as: device, inputs The controller is connected to the outputs of the x bits of the registers, the control inputs of which are connected to the clock input of the device, the group of request inputs of the device is connected to the group of inputs 35 of the frequency generator, -th- (i 1 ,,,., of) connected to the first elements of the codec And s The groups, the outputs of which are connected to the informational inputs of the 1st register, contain g 40 elements of SHP-NOT and - 2 elements of IL, with the i- and INPUT of the -th (, ..;) of the element OR-NOT connected to the output of the J-th bit of the i-th register, the output of the j-th element OR NOT is connected to the second 45 inputs of the j-th elements AND groups and with (nj T1) -th inputs of the elements OR from the first to (1) -th, output j th element OR is connected to (0 -} -t lJ-M input of the first element OR, the output of the first element 50 of the OR element is NOT connected to the first input of the second element SH1I-NOT,

The device is designed to work with a single flow flow.

The drawing is a diagram of the device,

The device contains groups of 1 elements AND, registers 2, encoder 3,

decoder 4, elements OR NOT 5, elements OR 6, clock input 7, query inputs 8, information outputs 9

The device works as follows.

In the initial state, registers 2 are zeroed (not shown) and at the output of the rj-ro element OR NOT there is a high level. As a result, at the outputs of all the OR elements - single signals, as a result of which the outputs of all the OR-NOT elements, except for the N-th, low levels are set. Consequently, only the P elements of the AND groups 1 are open.

The signal of the first application, one of the request inputs 8, is fed to the corresponding input of the encoder 3, the code from the outputs of which passes through the nth elements of the AND groups of 1 and records the first bits of the registers 2. As a result, the output of the hth element of the RSHL A zero signal does NOT appear, and at the output (ti-l) -ro of the W-SH-Element element, which opens (and-1) -th elements AND of groups 1; il elements and

are closed.

one

Sleep, code, conformance

following it, it is written into (tt-l) -e bits of registers 2. When this is done, (o-2) -e elements of AND groups 1, and (And |)) -e are closed. The filling of the KOflaNjH order of the remaining bits of registers 2 is similar. The number of. Bits in registers 2 must be different for the number of sources of requests, so that there is no situation where registers 2 are completely filled and the next application is received.

The application code from the outputs of the x bits of the registers 2 post-entry to the input of the decoder 4, as a result of which at one of the outputs 9 corresponding to the first incoming application, a signal appears. After its servicing, a pulse is applied to clock input 7, which is used to shift the contents of all registers 2 by one bit to the right. For service, the second application is accepted. If before the end of the service of the first application in registers 2, codes b were recorded. After the shift of the contents of the registers 2 at the output of the (n-k) -ro element -OR-NO, the zero signal is output, and at the output of the (n-k-t-l) -ro it is single. In the future, the device operates as described above.

Claims (1)

A DEVICE FOR ORGANIZING A QUEUE containing Eog'.j η groups of elements And (where η is the number of sources of applications), η registers, an encoder and a decoder, the group of outputs of which is a group of information outputs of the device, the inputs of the decoder are connected to the outputs of the x-th digits registers, the control inputs of which are connected to the clock input of the device, the group of request inputs of the device is connected to the group of inputs of the encoder, ί -th (1d 1, ..., fog '? П) the output of which is connected to the first inputs of the elements And the 1st group the outputs of which are connected to inputs of the 1st register, characterized in that, in order to reduce hardware costs, it contains L elements OR-NOT and η-2 elements OR, and the ί -th input j -th (j-1, ..., ”) of the OR-NOT element is connected to the output of the jth bit of the i-th register, the output of the jth element OR is NOT connected to the second inputs of the <elements of the groups and ((. Л-] + 1) ~ inputs of the elements tg OR from the first to the (j-1) th, the output of the j-th OR element is connected to the (Eo ^ n + O-th input of the j-th OR element, the output of the first OR-NOT element is connected to the second input of the second OR NOT. pharmacy 1 1126964