SU1164891A1 - Direct fibonacci code-to-inverse fibonacci code converter - Google Patents

Abstract

DIRECT FIBONACCER B REVERSE CONVERTER containing a n-bit register, where n is the code size of the converted code, pulse distributor, Fibonacci code reduction unit, the first group. the inputs of which are connected to the first output of the pulse distributor, the intakes of the inputs respectively to the outputs of the n-bit register, and the outputs of the elements AND groups are respectively connected to the information inputs of the Fibonacci coding block, the outputs of which are the outputs of the converter, and the control input of the block bringing the Fibonacci code to the minimum form is connected to the second output of the pulse distributor, characterized in that, in order to expand the class of solved problems, by providing These transformations, for any natural value of the p parameter of the Fibonacci code, introduced a group of (nr) OR elements, the outputs of which are respectively connected to the low-order n bits of the n-register, the high-bit inputs of which are connected to the logical zero input of the transducer i the input of the i-ro bit W whose (, ... n - 2p) through with the elements OR groups are connected to the input of 1-bit, where l (), ... ... (i + 2p), n- bit register inclusive, input j-ro bit converter, where - 2p 1,.,. ... (p-p), through the OR elements of the Ob group is connected to the input of the q-x bits, where q (j + p), .. ,, n) of the n-bit register, the input of the K-th bit transform CD 100 l (K p-p + 1,.,., p) through the elements of the group III connected to the input of the k-th bit of the n-bit register.

Description

The invention relates to computing and can be used to convert a direct p Fibonacci code to the inverse. The purpose of the invention is to expand the class of solvable tasks by providing the possibility of conversion for any natural value of the parameter p of the Fibonacci code. The drawing shows the functional diagram of the converter of the direct Fibonacci code to the inverse. The converter contains an n-bit register 1, a block 2 of minimizing p Fibonacci code to a minimum form a group of 3 elements AND, a distributor of 4 pulses, a group of 5 elements OR Register 1 is intended to receive through an OR element of group 5 a pre-converted direct Fibonacci code the conversion to the inverse p Fibonacci code and the issuance of p-straight and (p-p) -inverse

ABOUT

About 1

About About 1

I 1 values of the received code through the elements AND of group 3 to the inputs of block 2 of casting p of the Fibonacci code to the minimum form, which is intended for performing convolution operations of the n-bit code. The pulse distributor 4 is designed to control the operation of the converter. The Converter operates as follows. The forward p-bit Fibonacci p code to be converted is first converted as follows: The 1st bit of the direct p Fibonacci code is electrically driven through the OR elements to bits from (t + p) to (i + 2 p) inclusive The n-bit register I, and the most significant bits are set to zero. Examples of the preliminary transformation of the number 17 for p Fibonacci code with p.

Next, the pre-converted direct Fibonacci code goes into n-bit register 1 ..

The first control signal 50 from the distribution; pin 4 of pulses arriving at the elements AND of group 3 is used to output into the corresponding bits of the block 2 p-forward and (n) inverse values of the bits of the S5 I register. -. .

On the second signal from the distributor of 4 pulses, arriving at

clock input of block 2, the convolution of the Fibonacci code located there occurs.

After i end of the transient processes, the reverse outputs of the Fibonacci code will be generated at the information outputs of block 2.

The operation of the proposed device yo is illustrated by two examples in which the direct r Fibonacci codes with and are converted into inverse,

Weights. Source code - 5 Partially expanded The operation of the cast unit 4

Reverse 2 Fibonacci code of 5-13

p-3

Weights of bits Source code - 14 Partially expanded code

Job Block 4

Inverse 3-Fibonacci code of 14-4 The proposed Gimeet converter has a wider functionality due to the fact that it allows you to convert direct p Fibonacci codes for any p.

00000000

10 7 5 43 2 1 111

000 About 000000

001 I 1 10000

About 0000 About 1 111

000 10 о о 000

o 00100 000 o In addition, it has a simpler structure compared to the prototype type, since there is no higher-order definition block, and the i-transform time remains the same.

Г,, t ,, n-pr, -f, п

Claims (1)

DIRECT FIBONACHI DIRECT CONVERTER TO REVERSE, containing η-bit register, where η is the digit capacity of the converted code, a pulse distributor, a unit for reducing the Fibonacci code to a minimum form, a group of AND elements, the first inputs of which are connected to the first output of the pulse distributor, the second inputs respectively with outputs p-bit register, and the outputs of the elements AND groups are respectively connected to the information inputs of the block to bring the Fibonacci code to the minimum form, the outputs of which are the outputs of the converter I, and the control input of the unit for reducing the Fibonacci code to the minimum form is connected to the second output of the pulse distributor, characterized in that, in order to expand the class of problems / problems to be solved by providing the possibility of converting the Fibonacci code into any parameter introduced a group of (pr) OR elements, the outputs of which are respectively connected to the inputs of the least significant bits of the n-bit register, the inputs of the p highest bits of which are connected to the logic zero input of the converter horn (i = l, ... n - 2p) through the elements OR groups are connected to the input of 1-digits, where 1 = (i + p), ... ... (i + 2p), n-bit register inclusive, j-ro discharge input of the converter, where j = n - 2p + 1, ... ... (η-p), through the elements OR groups connected to the input of q-x bits, where 4 ⁼ (j ⁺ p), ···> n) n-bit register, the input of the K-th converter p-p + 1, ..., p) through the elements of the OR group is connected to the input of the k-th discharge of the p-bit register. II64891