SU1198533A1 - Device for simulating phase jitter of pulses of code sequence - Google Patents

Abstract

A DEVICE FOR MODELING THE PHASE DRAGGING OF CODES CONNECTION PULSE, containing a clock pulse generator, the output of which is connected to the input of the delay line and the trigger start input of the pseudo-random sequence, produced in the form of an annular shift register with feedback links and having K + 1 bits, which has K + 1 bits, which has K + 1 bits, which has KP 1 1 generator, and has chases that return, and has K + 1 bits. To the higher bits of which are connected respectively to the inputs of the element I, the block of forming code combinations, the output of which is the output of the device, characterized in that, in order to increase and accuracy of modeling and simplifying the device, it additionally contains a multiplexer, a reversible counter and an EXCLUSIVE OR element, the information inputs of the multiplexer are connected respectively to the outputs of the delay line, the control inputs to the discharge outputs of the reversible counter, and the output of the multiplexer is connected to the input of the code generation unit, the counting input of the reversible counter is connected to, the output of the clock pulse generator, the control input of the reversing counter's reverse is connected to the output (The first digit of the pseudo-random sequence and the first input of the STARTING element OR, 8 the reset input of the reversible counter e is connected to the output of the element I, and the prohibition input of the account of the reversible counter is connected to the output of the counter; this is the EXTERIOR IL, the second input of which is connected to the output older SP bit generator pseudo-random DO SAE sequence.

Description

one

This invention relates to a technique for simulating distortion of reproducible digital magnetic recording signals.

The purpose of the invention is to increase the modeling accuracy and simplify the device. I

Diagram of the device shown in the drawing.

The device contains a clock pulse generator 1, a delay line 2, a pseudo-random sequence generator 3, an AND 4 element, a code combination generation unit 5, a multiplexer 6, a reversible counter 7, an EXCLUSIVE SHSh 8 element.

During operation of the device, noise jitter of the pulse phase is modeled at the output of block 5 with the normal distribution law of the phase shift characteristic of digital magnetic recording signals. It is known that the sum of the voltages of a group of adjacent outputs of a pseudo-random sequence generator with a large number of bits corresponds to the normal distribution law. The summation in the device is carried out as follows. In the cycle, when logical zeroes appear at all K high bits of the generator 3, the element AND 4 resets the counter 7 k at its outputs it turns out to be a binary number equal to the sum of K single digits (in this case, K zeros) of the K high bits of the 3 generator Subsequently, with each next clock cycle, this number can either be changed by one to one side or the other, or it can be saved. Since every time this number is formed as a result of a shift in generator 3, the expected number in the next clock cycle for changing the sum of the outputs of generator 3 can be determined in the current clock cycle.

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For this purpose, the EXCLUSIVE OR element is used, which, in the case where the sum does not have to change (the logical state of the low-order and high-order bits of generator 3 are the same), prohibits a change in the state of the counter. Otherwise, the counter in the next generator clock I increments by one or

O in the direction of addition, or in the direction of subtraction. The counting direction specifies the content of the low bit of generator 3. It is easy to check that the outputs of counter 7 always form a number equal to the total number of units at the senior outputs of generator 3. Brute force following the zero state of the generator 3 a statistical quantity with a normal distribution.

The generator 1 continuously generates a sequence of clock pulses of a fixed frequency, which are fed to the inputs of the generator 3, the counter .7 and the delay line 2. The next clock pulse changes in accordance with the algorithms of operation of the state of the counter 7 and changes the state of the outputs of the generator 3. At the same time, the multiplexer 6, controlled by the counter 7, connects to the input of the shaping unit 5

35 code combinations one of the outputs of the delay line. The number of the switched output of the delay line is equal to the binary number at the output of the counter 7, i.e. amount. To the adjacent outputs of the generator 3. Thus, the phase of the pulse at the output of the multiplexer 6 is also a random variable with a normal distribution. Block 5 encodes the output of the device.

45 sequence of pulses.

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eight

Claims (1)

DEVICE FOR MODELING PHASE SHAKING OF CODE SEQUENCE PULSES, containing a clock pulse generator, the output of which is connected to the input of the delay line and the start input of the pseudorandom sequence generator, made in the form of a circular shift register with feedbacks and having K + 1 bits, the outputs of which are connected respectively, to the inputs of the element And, the block for generating code combinations, the output of which is the output of the device, characterized in that, in order to increase the accuracy of In order to simulate and simplify the device, it additionally contains a multiplexer, a reverse counter, and an EXCLUSIVE OR element, the information inputs of the multiplexer being connected respectively to the outputs of the delay line, the control inputs to the bit outputs of the reversing counter, and the output of the multiplexer connected to the input of the code combination generation unit the input of the reverse counter is connected to the output of the clock generator, the input of the reverse control of the reverse counter is connected to the output of the first bit and a pseudorandom sequence generator and the first input of the EXCLUSIVE OR gate, the reset input of down counter connected to the output of the AND and the input prohibition counting down counter connected to the output of the EXCLUSIVE OR, the second input of which is connected to the output of the most significant bit of the pseudorandom sequence generator. > * 1198533