SU1569828A1 - Generator of flow of pseudo-random numbers - Google Patents

Abstract

The invention relates to the field of computing and can be used in static modeling problems and to simulate random signals. The aim of the invention is to increase the period of generated pseudo-random numbers with certain correlation properties and a one-dimensional probability distribution function. The pseudo-random number stream generator contains a clock pulse generator, pulse distributor, register, T-flip-flop, D-flip-flop, first and second binary counters, three adders, the outputs of which form the output of the generator. The purpose of the invention is achieved by using different ways of forming the three components of the generated number, each of which is obtained at the output of the corresponding adder. 1 il.

Description

The invention relates to computing and can be used in problems of a static model, a title, and to simulate random signals.

The purpose of the invention is to increase the period of generated pseudo-random numbers with certain correlation properties and a one-dimensional probability distribution function.

The drawing shows a block diagram; generator.

The pseudo-random number stream generator includes 1 clock pulse generator, 2 pulse distributor, register 3, T-flip-flop 4, D-flip-flop 5, binary counters 6 and 7, adders 8-10, and generator output 11 form the outputs of all three adders 8 - ten.

The pseudo-random number stream generator works as follows.

The clock pulse generator 1 generates a reference sequence of pulses arriving at the input of the distributor 2 pulses, to the counting input of the T-flip-flop 4, a clock input of the D-flip-flop 5 and the counting input of the first binary counter 6. At the first output of the distributor 2 pulses every k4 clock a pulse appears a short pulse arriving at the input of the recording resolution of register 3. This signal is used to write the contents of the third adder 10 to the register 3 in parallel. Consequently, the number in register 3 can change bc every D cycles of operation. T-flip-flop 4 with the arrival of each clock pulse changes its state SP

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In other words, the inverse of the output of the t-flip-flop 4 is connected with the input of the inversion control of the output code of the register 33, therefore, depending on

The T state of the T-flip-flop 4 is either the same as the code of the number stored in the register, or the return code of this Isla is output. A similar change in the output code of register 3 will occur with the arrival of each successive clock pulse. Positive front

the pulse from the inverse output of the T-flip-flop 4 acts on the counting input of the second binary counter 79 increasing its content by one each time. Such an increase continues until the counter 7E is completely filled when a signal appears at its output of the end of the count with a logic level O instead of a signal with a logic level that has occurred up to this point. By the next clock pulse arriving at the clock input of D-flip-flop 5, D-flip-flop 5 will copy this signal, as a result of which from state 1 it will go to state O. As a result of such a transition, an inverse output of D-flip-flop 5 will appear impulses affecting the input of the binary counter 7 write control input. By this impulse The census of the output code of register 3 is carried out into the counter. As a result of changing the contents of the counter 7, the signal at its output of the end of the count changes oppositely, i.e. the D-flip-flop will also go into one state for a signal with a logic G 3 level at the next clock pulse and a zero signal will occur at its inverse output. Thereby, the operation of presetting the counter 7 is completed and it again continues operation in the pulse counting mode at the counting input,

The clock pulses from the clock generator to the counting input of the first binary counter 6 increase its content to the limit value 1-1, where 1 is the selected conversion factor of counter 6, after which the counter returns to the initial zero state and begins to fill again .

Adders 8 - 10 sum the input codes: first total 1

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Matrix 8 sums a one-bit signal from the inverse output of the T-flip-flop 4, a code of the s discharge outputs of the counter -7 and an output code of the 3S register the second adder 9 sums up a one-bit signal from the direct output of the T-flip-flop 4, a code from the distant outputs counter 6 and the output code of register 3, the third adder 10 sums the output codes from the first adder 8 and the second adder, 9, as well as a one-bit signal generated at the second output of the distributor 2 pulses. This signal is a positive pulse occurring after k2 clock pulses (kg-dc ,,) after the appearance of a pulse on the first output of the pulse distributor 2 and the duration of (,) clock cycles, i.e. until the moment of occurrence of the next pulse at the first output of the distributor 2,

For correct operation of the pseudo-random number flow generator, the bit width of adders 8-10, register 3 and second counter 7 must be the same. In this case, as a result of summation, a code is taken that corresponds to the youngest sp of the resulting sum. In addition to this, you should choose k, s "

The output of the generator 11 of a stream of pseudo-random numbers form the outputs of adders 8-10. Therefore, a sequence of (3T) -sized binary numbers can be formed at your route. The generator can also be used as a three-channel generator of correlated m-bit pseudo-random numbers,

The use of different ways of forming the three components of the generated number 9 of the first, second and third adders formed at the outputs allows increasing the period of the resulting pseudo-random sequence of numbers.

Analysis of the probability properties of numerical sequences; generated at the output of this generator using the statistical modeling method (model parameters,,, m 3; 4 | 5), allows to establish that the generated numbers have an approximately uniform distribution with a rapidly decaying monotonic autocorrelation function. As m increases, the degree of uniformity of the distribution and the decay rate of the correlation function increase.

Claims (1)

Invention Formula A pseudo-random number flow generator, comprising a clock pulse generator and a register, characterized in that, in order to increase the period of generated pseudorandom numbers, a pulse distributor, T-flip-flop, D-flip-flop, first and second binary counters, three adders, moreover, the output of the clock pulse generator is connected to the counting inputs of the T-trigger and the first binary counter, to the clock input of the pulse distributor and the clock input of the D-trigger, the inverse output of which is connected to the record resolution input and a second binary counter, a terminal count output of which is connected to the D-input of D-flip-flop, and the time regular outputs - with the first input of the first 25 15 five Inverted output (T-flip-flop is connected to the second input of the first adder, to the counting input of the second binary counter and the control input of the inversion of the output register code, the bit outputs of which are connected to the information input of the second binary counter, to the third input of the first and the first input of the second adders, the outputs of which are connected respectively to the first and second inputs of the third adder, the output of which is connected to the information input 5 of the register, the first and second outputs of the pulse distributor The inputs of the first binary counter are connected to the second input of the second adder, the third input of which is connected to the direct output of the T-flip-flop, the output of the generator is formed by the outputs of the first, second and third adders. 0