RU2012054C1 - Device for exhaustion of permutations - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has two decoders, two multipliers, two OR gates, group of n adders where n is maximal length of generated permutations, n division units, two groups of n registers, three groups of delay gates and group of AND gates. Device implements algorithm for conversion of m(0≅ m<k) into corresponding permutation of elements (k≅ n). EFFECT: increased field of application due to generation of permutations having variable length. 1 dwg

Description

 The invention relates to computer technology, is intended for the formation of permutations of variable length and can be used to solve a wide class of combinatorial problems in various fields of science and technology (see, for example, Kureichik V.M., Glushan V.M., Scherbakov L. I. Combinatorial Hardware Models and an Algorithm in CAD (Moscow: Radio and Communications, 1990, p. 216).

 Known devices that provide the generation of permutations of the original values (see, for example, ed. St. USSR NN 957215, 995093, 1124319, 1180917, 1190388, 1397933, etc.). The disadvantage of these devices is the inability to control the sequence of generated permutations.

 Closest to the technical nature of the claimed is a device for enumerating permutations containing a control unit and a decoding unit (see ed. St. USSR N 1410056, class G 05 F 15/20, 1988). This device implements a procedure for converting a permutation number into a unique permutation corresponding to it. The disadvantages of the device are the dependence of the functional diagram on the number of rearranged elements and the impossibility of generating permutations of variable length.

 The purpose of the invention is the expansion of the scope by providing the generation of permutations of a variable number of elements.

 The essence of the invention lies in the fact that in a device containing a group of division blocks, a block for selecting a minimum number, two groups of registers, a group of adders, the first and second elements OR, a register, a decoder and two groups of delay elements, a register, the first and second demultiplexers are entered, two groups of OR elements, a group of delay elements, a group of first and second AND elements, a group of triggers, a register, and a decoder. In this case, the information output of the entered register is connected to the information input of the decoder and the control inputs of the demultiplexers, the information input of the first demultiplexer is connected to the start input of the device, and its outputs are connected to the inputs of the corresponding elements of the first group, the information input of the second demultiplexer is connected to the output of the register, and its outputs connected to the inputs of the corresponding OR elements of the second group, the outputs of the OR elements of the first group are connected to the inputs of the delay elements of the first group py, and the outputs of the OR elements of the second group are connected to the information inputs of the division blocks, the decoder outputs are connected to the input of the first element and the inverse input of the second element of the group, the other inputs of the AND elements are combined with the read input of the corresponding adders and the inputs of the register of the group registers and connected to the output of the corresponding element delays of the third group, the input of which is connected to the output of the corresponding delay element of the second group, the inputs of which are connected to the output of the second element AND of the group, and the outputs are not The output elements AND groups are connected to the inputs of the first OR element, the output of the OR element is connected to the combined zero inputs of the triggers, the inverse outputs of which are connected to the reading inputs of the group registers, and the single inputs are connected to the outputs of the decoder, the information outputs of the group registers are connected to the inputs of the minimum number selection block .

 Functional diagram of the device shown in the drawing.

, где n - предельное число элементов перестановок), схему 5 выбора минимального числа и дешифратор 6. Блок 2 декодирования предназначен для преобразования заданного натурального числа в соответствующую ему перестановку требуемого числа элементов. Блок содержит элементы 7_i, i=

, 8_i, i=

, 9_i, i=

задержки регистры 10, 11, 12, i=

, демультиплексоры 13, 14, дешифратор 15, элементы ИЛИ 16, 17, 18_i, 19_i, i=

, группу первых и вторых элементов И 20_i, i=

, блоки 21, i деления, сумматоры 22_i, i=

.The device comprises a control unit 1 and a decoding unit 2. Block 1 is designed to form a defining set of numbers in accordance with the selected permutation option and the device operation step, select the minimum number from this set and supply it to the input of the decoding unit. Block 1 contains registers 3 _i , triggers 4 _i (i =

, where n is the limit number of permutation elements), a minimum number selection circuit 5 and a decoder 6. Decoding unit 2 is designed to convert a given natural number into a corresponding permutation of the required number of elements. The block contains elements 7 _i , i =

, 8 _i , i =

, 9 _i , i =

delay registers 10, 11, 12, i =

, demultiplexers 13, 14, decoder 15, elements OR 16, 17, 18 _i , 19 _i , i =

, the group of first and second elements And 20 _i , i =

, blocks 21, i divisions, adders 22 _i , i =

.

.The device also has information inputs 23, 24, input 25 start and information outputs 26 _i , i =

.

 The operation of the device is based on the implementation of the procedure for converting the initial number m (0≅ m <k! K≅ n) into a uniquely corresponding permutation of the initial numbers, previously numbered 1, 2,. . . , k elements (see Babaev A. A. Procedures for Encoding and Decoding Permutations. Cybernetics, 1984, N 6, pp. 75-76).

вносятся числа исходного определяющего множества I_o= { 1,2, . . . , n} , причем число Р(Р∈I_о) вносится в регистр 3_р, в регистр 11 по входу 23 вносится число переставляемых элементов К≅ n, а в регистр 12 по входу 24 вносится число m(0≅ m≅ k ! ). При этом код числа К с информационных выходов регистра 11 поступает на вход дешифратора 15 и появляется сигнал единичного уровня на К-м управляющем выходе дешифратора, с которого он поступает на инверсный вход первого и вход второго элементов И 20_к. Триггеры 4_i, i=

, находятся в исходном нулевом состоянии. Сигналы с их нулевых выходов поступают на считывающие выходы регистров 3_i, i=

, и числа исходного определяющего множества I_о с информационных выходов регистра 3_iпоступают на соответствующие входы схемы 5 выбора минимального числа. Код минимального из чисел исходного определяющего множества с выхода схемы 5 поступает на объединенные первые информационные входы сумматоров 22_i, i=

.Before working in registers 3 _i, i =

the numbers of the original defining set I _o = {1,2,. . . , n}, moreover, the number Р (Р∈I _о ) is entered in the register 3 _p , the number of permutable elements К≅ n is entered in the register 11 at the input 23, and the number m (0≅ m≅ k! ) In this case, the code of the number K from the information outputs of the register 11 goes to the input of the decoder 15 and a signal of a unit level appears on the K-th control output of the decoder, from which it goes to the inverse input of the first and the input of the second elements And 20 _k . Triggers 4 _i , i =

are in the initial zero state. The signals from their zero outputs go to the reading outputs of registers 3 _i , i =

, and the numbers of the initial determining set I _о from the information outputs of the register 3 _i are supplied to the corresponding inputs of the minimum number selection circuit 5. The code of the smallest of the numbers of the initial determining set from the output of circuit 5 goes to the combined first information inputs of adders 22 _i , i =

.

The operation of the device begins with a positive start pulse at input 25 of the start of the device. In this case, the trigger pulse is fed to the read input of register 10 and to the information input of demultiplexer 13, from the information outputs of register 10, the code of the number m is sent to the information input of demultiplexer 14. From the K-th output of demultiplexer 13, the signal goes to the input of OR element 18 _k , and with To the output of the demultiplesor 14, the code of the number m goes to the input of the OR element 19 _k . From the output of the OR element 18 _{k, the} trigger pulse is supplied to the control input of the division block 21 _k , and from the output of the OR element 19 _{k, the} code of the number m is fed to the information input of the division block 21 _k .

, осуществляют деление числа, поступающего на их информационный вход, на модуль r_i= n-i+1. При этом с первого выхода блока деления выдается целая часть от деления поступающего на его вход числа на соответствующий данному блоку постоянный модуль, а с второго - остаток от деления. Поэтому при поступлении на управляющий вход блока 21_k деления импульса в нем осуществляется деление числа m на постоянный модуль r_k= n-K+1. Целая часть от деления поступает с первого выхода блока 21_k на вход элемента ИЛИ 19_k-1, а остаток от деления с второго выхода поступает на второй информационный вход сумматора 22_k. С выхода элемента ИЛИ 19 целая часть от деления поступает на информационный вход блока деления 21_k.Blocks 21 _i divisions, i =

divide the number arriving at their information input by the module r _i = n-i + 1. At the same time, the integer part from dividing the number arriving at its input by the constant module corresponding to the given block is issued from the first output of the division block, and from the second - the remainder from division. Therefore, when a pulse division is received at the control input of the block 21 _{k, the} number m is divided into a constant module r _k = n-K + 1. The integer part of the division comes from the first output of block 21 _k to the input of the OR element 19 _k-1 , and the remainder of the division from the second output goes to the second information input of the adder 22 _k . From the output of the OR element 19, the integer part of the division goes to the information input of the division unit 21 _k .

, осуществляется выделение целой части и остатков от деления на постоянный модуль чисел, поступающих с первого выхода блоков 21_i деления, i=

, соответственно. Через время t₁= k . τ₁ от момента подачи импульса запуска на вход 25 пуска импульс с выхода элемента 7_i задержки поступает на вход элемента 9₁ задержки и управляющий вход сумматора 22₁, и в нем осуществляется сложение числа, поступившего с второго выхода блока 21₁деления, с числом, поступившим от схемы 5 выбора минимального числа.After a delay time τ ₁ sufficient for dividing and transmitting the results, a pulse appears at the output of the delay element 7 _k , from where it passes through the OR element 18 _k-1 to the control input of the division block 21 _k-1 and the input _{of the} delay element 7 _k-1 . Further, it is similarly sequentially through the time interval τ _{1 by} blocks 21 _i , i =

, the whole part and the remainder from dividing by a constant modulus of the numbers coming from the first output of the division blocks 21 _i , i =

, respectively. After time t ₁ = k. τ ₁ from the moment the trigger pulse is input to the trigger input 25, the pulse from the output of the delay element 7 _i arrives at the input _{of the} delay element 9 ₁ and the control input of the adder 22 ₁ , and the number from the second output of the division unit 21 _{1 is} added to the number received from the circuit 5 select the minimum number.

, принадлежит к множеству первых K чисел натурального ряда), и сигнал с соответствующего управляющего выхода дешифратора поступает на единичный вход соответствующего триггера 4_i, i=

. Триггер переходит в единичное состояние, снимается сигнал со считывающего входа соответствующего регистра 3_i, i=

, чем моделируется изменение определяющего множества чисел, и на выходе схемы 5 появляется код минимального числа, соответствующего данному измененному определяющему множеству.After a delay time τ ₂ sufficient for the adder to operate, a signal is output from the delay element 9 ₁ to the read input of the adder 22 ₁ , a register write enable input 12 _1, and the combined inputs of the first and second elements And 20 ₁ . The sum code from the output of the adder 22 ₁ goes to the information input of the register 12 ₁ and the corresponding input of the OR element 17. From the output of the OR element 17, the sum code goes to the input of the decoder 6 of block 1, and from the output of the second element And 20 the pulse goes to the input of the element 8 ₂ delays. In the decoder 6, the sum code is decrypted (the amount at the output of the adder 22 _i , i =

, belongs to the set of the first K numbers of the natural series), and the signal from the corresponding control output of the decoder goes to the single input of the corresponding trigger 4 _i , i =

. The trigger goes into a single state, a signal is taken from the reading input of the corresponding register 3 _i , i =

what simulates the change in the defining set of numbers, and at the output of circuit 5, the code for the minimum number corresponding to this changed defining set appears.

, и считывающие входы регистров 12_i, i=

. Числа, соответствующие полученной перестановке, поступают с информационных выходов регистров 12_i, i=

, на информационные выходы 26_i, устройства i=

.After the delay time τ ₃ , longer than the duration of the start pulse, a signal appears at the output _{of the} delay element 8 ₂ and is supplied to the input _{of the} delay element 9 ₂ and the control input of the adder 22 ₂ . Further operation of the circuit is similar, and after a time t ₂ = K τ ₂ + (K-1) τ ₃ + t ₁ from the moment the start pulse is applied, a signal appears at the output of the delay element 9 _k , from where it arrives at the combined inputs of the I20 _k elements. Since the signal from the k-th output of the decoder 15 is present at the direct input of the first and at the input of the second element And 20 _k , the signal at the output of the first element And 20 _k does not appear, and the signal from the output of the second element And 20 _k goes to the corresponding input element OR 16 and from its output goes to the combined zero inputs of the triggers 4 _i , i =

, and the reading inputs of the registers 12 _i , i =

. The numbers corresponding to the obtained permutation come from the information outputs of the registers 12 _i , i =

, to information outputs 26 _i , devices i =

.

 Thus, the proposed device provides the formation of permutations of not a deterministic number of elements n, but a variable number of elements K ≅ n, defined by the user. This indicates a significant expansion of functionality achieved in comparison with the prototype and the achievement of the purpose of the invention.

Claims (1)

 A device for enumerating permutations, containing the first register, the group of information inputs of which is a group of information inputs of the device, and the input for enabling data reading is connected to the device start input, the first and second groups of n registers (n is the maximum permutation length), a group of n division blocks, a group n adders, the minimum number selection block, the first and second elements OR, two groups of n delay elements and the first decoder, the group of information outputs of the registers of the first group is connected to the input group in the minimum number selection block, the output of which is connected to the first input of the group adders, the second adder input is connected to the output of the corresponding group division unit, and the outputs of the group adders are connected to the inputs of the corresponding registers of the second group and the corresponding inputs of the first OR element, the output of which is connected to the input of the first the decoder, the output of the second OR element is connected to the input enable reading registers of the second group, the outputs of which form a group of information outputs of the device, different we note that, in order to expand the scope by providing generation of permutations of variable length, the first and second groups of (n - 1) th OR elements, the second register, the second decoder, the first and second demultiplexers, the third group of (n - 1) of the delay elements and a group of n pairs of AND elements, a group of n triggers whose zero outputs are connected to the read permission inputs of the registers of the first group, the zero inputs of the group triggers are combined and connected to the output of the first OR element, and the unit inputs are connected s with the corresponding outputs of the second decoder, the information input of the second register is connected to the information input of the device, and the output is connected to the input of the second decoder and the control inputs of the first and second demultiplexers, the information input of the first demultiplexer is connected to the start input of the device, the nth output of which is connected to the control the input of the nth division block and the input of the nth delay element of the first group, the group of outputs of the first demultiplexer is connected to the first inputs of the corresponding elements OR per group, the second inputs of which are connected to the outputs of the subsequent delay element of the first group, respectively, and the output of each OR element of the first group is connected to the control input of the corresponding division unit and the input of the corresponding delay element of the first group, the outputs of the delay elements of the second group are connected to the first inputs of the corresponding pairs of elements And the group, with the permission input to read the result of the adders of the group and the input permission to write the corresponding registers of the second group, the second input of the second email ment And performed inverse, and the second input of the first element And of each pair of elements And groups are connected to the outputs of the second decoder, the output of the second element And of each pair of elements And groups, except the last, is connected to the input of the corresponding delay element of the third group, the output of which is connected to the clock the input of the group adders and the input of the corresponding delay element of the second group, the outputs of the first elements AND pairs of elements AND groups are connected to the corresponding inputs of the second OR element, the input of which is connected to the output of the second element AND of the nth pair of elements of the AND group, the information input of the second demultiplexer is connected to the output of the register, the n-th output of the second demultiplexer is connected to the information input of the n-th block of division of the group, and the group of outputs of the second demultiplexer is connected to the first inputs of the corresponding elements OR of the second groups, the outputs of which are connected to the information inputs of the corresponding division unit, and the second inputs of the OR elements of the group are connected to the outputs of the subsequent units of the division of the group, respectively.

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