RU2620725C2 - Device for forming spoofing resistant nonlinear recurrent sequences - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: method is carried out by forming different dictionaries of the non-linear recurrent sequences for different code dictionaries and their software change during the operating duration of L=12. The process of forming non-linear recurrent sequences (NLRS) and non-linear recurrent noninverse-isomorphic sequences (NLRNIS) is carried out in such a way, that new NLRS will be formed every 12 cycles, shifted by 3 characters to the left, and then the new dictionary digit code is written, providing the formation of these NLRS and NLRNIS dictionaries, in which every subsequent NLRS and NLRNIS will differ from the previous ones by left shifting of the cycles.

EFFECT: expansion of functionality.

3 dwg

Description

The invention relates to techniques for generating discrete signals used in communication and radar systems with complex noise-like signals (SHPS).

The closest in technical essence to the claimed invention and adopted as a prototype is a device for forming nonlinear recurrent sequences of discrete signals (see AC 1457650 USSR, MKI G06F 15/20). Device for forming nonlinear recurrence sequences [Text] / Snytkin II, Gorbenko ID, Litvinenko PT (THE USSR). - 4,239,614 / 24-24; declared 05/04/87). It contains an adder modulo two, a delay element, a first element AND, a shift register, the corresponding inputs of which are connected to the corresponding outputs of the control unit, an adder modulo two, the output of which is connected to the input of the shift register entry, and the first adder modulo two is connected respectively with the output of the delay element, the input of which is connected to the output of the four-input first element And, the fourth input of which is connected to the first inverse output of the shift register, a control unit consisting of the first and second counters, key, clock, OR element, first and second registers, where the outputs of the first register are connected to the corresponding outputs of the control unit, and the inputs from the first to fourth of the first group of the control unit are respectively connected to the inputs of the “Initial phase code” of the device, the first the input of the initial phase code of the device is combined using the INSTALL OR element with the first direct output of the shift register and connected to the first information input of the first group of the control unit, the second input of the start code The first phase of the device is combined using the INSTALL OR element with the second direct output of the shift register and connected to the second information input of the first group of the control unit, the third input of the initial phase code of the device is combined using the INSTALL OR element with the third direct output of the shift register and the third adder modulo two and is connected to the third information input of the first group of the control unit, the fourth input of the initial phase code of the device is combined using the INSTALL OR element with the fourth direct output the shift register, the first input of the first element And, the second input of the adder modulo two and connected to the fourth information input of the first group of the control unit, the first inverse output of the shift register is connected to the fourth input of the first element And, the first, third, fifth and seventh outputs of the shift register are direct, and the second, fourth, sixth and eighth outputs of the shift register are the inverse outputs of the first, second, third and fourth bits, respectively, the first, third, fifth and seventh outputs of the shift register are connected with correspondingly to the first, second, third, and fourth buses of the first input of the control unit, the first output of which is connected to the first sync input of the second counter and the output of the OR element, the first input of which is connected to the first information input of the key, with the first sync input and the second counting input of the first counter, with the output of the pulse generator, the input of which is connected to the second input of the OR element, the second clock input of reading both memory registers, the second output of the “unlocking” key and the start input of the control unit, the third input of which It is connected to the first sync inputs of recording of both registers, the third input of "locking" the key and the output of the second counter, the second counting input of which is connected to the output of the key, and the first input of which is connected to the output of the OR element, the four inputs of the preset of the second counter are connected respectively to the four outputs the second memory register, four information inputs of which are connected respectively to the four buses of the fourth input of the control unit.

This prototype device provides the formation of various code dictionaries of nonlinear recurrence sequences and their program change during operation with a duration of L = 11. However, this prototype device does not provide the formation of various dictionaries of nonlinear recurrence sequences and their program change during operation with a duration of L = 12. To increase the noise immunity and immunity, it is necessary to be able to form various code dictionaries of nonlinear recurrence sequences and their program change during a longer duration operation, one of these durations is the duration L = 12.

The aim of the invention is the expansion of functionality through the formation of various dictionaries of nonlinear recurrence sequences (NLRP), which provides the formation of various code dictionaries and their program change during operation with a duration of L = 12.

The operation of the device can be divided into two cycles: the formation of one NLRP and one non-inverse isomorphic NLRP - NLRP (NI) and the formation of dictionaries NLRP and dictionaries of non-inverse isomorphic NLRP - NLRP (NLRP).

The device comprises: a shift register, the corresponding inputs of which are connected to the corresponding outputs of the control unit, an adder modulo two, the output of which is connected to the input of the shift register entry, and the first adder modulo two is respectively connected to the output of the delay element, the input of which is connected to the four-input output the first element And, the fourth input of which is connected to the first inverse output of the shift register, a control unit consisting of the first and second counters, key, clock generator, OR, first and second registers, where the outputs of the first register are connected to the corresponding outputs of the control unit, and the inputs from the first to fourth of the first group of the control unit are respectively connected to the inputs of the “Initial phase code” of the device, and the first input of the initial phase code of the device is combined using MOUNTING OR element with the first direct output of the shift register and connected to the first information input of the first group of the control unit, the second input of the initial phase code of the device is combined using the element MOUNTING OR with the second direct output of the shift register and connected to the second information input of the first group of the control unit, the third input of the initial phase code of the device is combined using the element INSTALLING OR with the third direct output of the shift register, the third input of the adder modulo two and connected to the third information input of the first group of the control unit, the fourth input of the initial phase code of the device is combined using the ASSEMBLY OR element with the fourth direct output of the shift register, the first input of the first AND element, the second input of the adder is modulo two and is connected to the fourth information input of the first group of the control unit, the first inverse output of the shift register is connected to the fourth input of the first element And, the first, third, fifth and seventh outputs of the shift register are direct, and the second, fourth, sixth and the eighth shift register outputs are the inverse outputs of the first, second, third and fourth bits, respectively, the first, third, fifth and seventh outputs of the shift register are connected to the first, second, third and fourth, respectively the buses of the first input of the control unit, the first output of which is connected to the first clock input of the second counter and the output of the OR element, the first input of which is connected to the first information input of the key, with the first clock input and the second counting input of the first counter, with the output of the pulse generator, the input of which is connected to the second the input of the OR element, the second clock input of reading both memory registers, the second output of the "unlocking" of the key and the start input of the control unit, the third input of which is connected to the first clock inputs of both registers, the third input of "locking" the key and the output of the second counter, the second counting input of which is connected to the output of the key, and the first input of which is connected to the output of the OR element, the four inputs of the preset of the second counter are connected respectively to the four outputs of the second memory register, four information inputs which are connected respectively to the four buses of the fourth input of the control unit, the following are entered into the external logic unit: instead of a two-input OR element, a three-input OR element is introduced and, in addition, the three-input element And is one, and the first direct output of the shift register is connected to the first input of the second and fifth elements And, the first input of the second element OR, the second direct output of the shift register is connected to the first input of the third element And, the third direct output of the shift register is connected to the third input of the fifth AND element, the output of which is connected to the third input of the third OR element, the fourth direct output of the shift register is connected to the second inputs of the second and fourth elements AND, respectively, the second inverse register output with the motor is connected to the third input of the first element And and to the second input of the fifth element And, the third inverse output of the shift register is connected to the second input of the first element And, the first input of the fourth element And, the output of which is connected to the first input of the third element OR, the output of which is non-linear the device’s recurrence sequence, to the second input of the second OR element, the output of which is connected to the second input of the third AND element, whose output is connected to the second input of the element NOT, the inverse output of the second ementa and connected to the first input of the first OR gate and a second input of NOT circuit whose output is the inverted output of the nonlinear device recurrent sequence.

Changes made to the device correspond to the signs of “significant differences” and provide the ability to form various code dictionaries of nonlinear recurrence sequences and their program change during operation with a duration of L = 12.

The invention is illustrated by drawings.

In FIG. 1 is a functional diagram of a device for generating simulated non-linear non-linear recurrence sequences, comprising: an adder modulo two 1, shift register 2, first, second, third, fourth and fifth, respectively 3, 5, 7, 8, 9, I elements, delay element 4, the first, second and third, respectively 6, 10, 11, OR elements, as well as the elements of the control unit included in the device, the first and second registers 12 and 14, the first and second counters 13 and 16, the key 15, the OR element 17 and generator 18, with corresponding links.

In FIG. 2 presents a table of the truth of the state of the device, which explains its work on the formation of one form of a nonlinear recurrence sequence of duration L = 12.

In FIG. Figure 3 shows the logical function of the device, synthesized and minimized using the Carnot map method.

Internal logic

Xb = {010110111000}

Xv (none) = {00011110110}

External logic BFOP:

Optimal in its properties and characteristics of pseudorandom sequences (PSP) of duration L = 12 is the position code (μ) of quadratic residues with a two-level periodic autocorrelation function Rμ (m) = 12, m ≠ 0, (mod 12), the construction of which is based on the use of the character ψ (•) of the multiplicative group of the field GP (p = 12).

A nonlinear recurrence sequence (NLRP) of length L = 12 has the form μ * = 010110111000, and a non-inverse isomorphic NLRP has the form μ _ni * = 00011110110.

The use of this NLRP provides in addition to noise immunity and cryptographic stability. The possibility of using NLRP dictionaries of a given duration, built on the basis of automorphic, noninverse-isomorphic and isomorphic transformations of the original NLRP (μ) using the program principles for changing NLRP in one dictionary, changing the NLRP dictionaries themselves, provides even greater imitability, cryptographic stability and secrecy of special communication systems.

Formation of NLRP

At the first clock moment, the source initial phase code for the status of the bits in register 2 is received at the device input, but the code is previously written to the register 14 using the “Record initial state” clock pulse supplied to the input record of the initial state of the device. At the second clock moment, the “Start of operation” pulse arrives at the start input, which, having passed to the input of the generator 18, turns it on, and also, having passed to the read input of register 14, provides the code for the initial phase is written off from register 14 to register 2, and passing through OR element 17 to the input of the register 2 register, provides the entry of the initial phase code into register 2. At the same time, the initial initial phase code appears at the outputs 3, 4, 5, 6 of register 2.

In the following clock periods, from the third to the fifteenth pulses from the generator 18, received at the input of the register 2 through the OR element 17, provide a sequential change in the status of the bits of the register 2 in accordance with the internal logic function so that, starting from the fifteenth cycle, the status of the bits of the register 2 are repeated. Thus, with a period of L = 12, a repetition of the register discharge states is provided. In this case, the formation of optimal SRP (NLRP) X _β = μ = (010110111000) and X _{β (none)} = μ: = (00011110110) with a duration of L = 12 is provided using elements And 5, And 7, And 8, And 9 and elements OR 6, OR 10 and OR 11.

The operation cycle can be repeated, starting from the fifteenth clock moment, using the “dictionary code code”, supplied to the input of the device code.

Consider the mode of formation of a certain type of NLRP dictionary. The volume of the NLRP dictionary, like any other dictionary of code recurrence sequences (including LRS), is determined by the number of autoisomorphic transformations.

The formation of a certain type of dictionary of NLRP and a dictionary of noninverse-isomorphic NLRP-NLRP-NLRPNI is as follows. The volume of the NRLP dictionary, like any other dictionary of code RPs, is determined by the number of auto- and isomorphic transformations. For NLRP L = 12, there are two non-inverse isomorphisms, the rest (18) are automorphic transformations, which are cyclic shifts of each non-inverse isomorphism. In our case, non-inverse isomorphisms are NLRP X _β = (010110111000) and X _{β (none)} = (00011110110), the formation of which is provided by the device at the initial phase of register 2 "1000".

To form other (automorphic) NLRPs, following the truth table in FIG. 2, it is enough to ensure the beginning of the formation of NLRP not from the initial phase “1011”, but from the initial phase such that corresponds to any intermediate state of the bits of register 2 (according to the truth table, this corresponds to measures from the third to the fourteenth). The choice as the initial phase of any intermediate state of register 2 (according to the truth table) does not violate the cyclic operation (with a period L = 12) of register 2, since it does not depend on the quality (structure) of the initial phase from the volume (set) defined in the truth table initial phases (intermediate register distances 2).

The nature of the dictionaries of NLRP and NLRPNI, therefore, depends on which initial phase is set in register 2 after any specific (previous) NLRP and NLRPNI have been formed. The order of alternation (selection) of the initial phases thus determines the form of the formed dictionaries NLRP and NLRPNI. They can consist only of one constantly formed NLRP and NLRPNI, only of two constantly formed NLRP and NLRPNI, only of three NLRP and NLRPNI, etc. and finally out of the twelve NLRP and NLRPNI. Thus, the order of alternation (selection) of the initial phases is thus laid down the properties of imitostability, cryptographic stability of the dictionaries NLRP and NLRPNI. The more complicated this alternation order, the higher the imitostability, cryptographic stability of the dictionaries NLRP and NLRPNI. Optimal in this sense are dictionaries constructed using such an order of alternation of NLRP, which is pseudo-random in nature. However, in any particular case determined by the operating conditions, it should be possible to change this order. These capabilities are implemented in the device by storing in the register 14 the intermediate state of the register 2 in accordance with the code of the dictionary code supplied to the input of the code of the device cipher.

In the 1st step, the operator enters the digit code 8 (1000) at the input of the device cipher code. This means that in register 2, after the start of the formation of the first NLRP, the third intermediate state of register 2 will be filled (in our case, it will be state 0110 of register 2 at the 5th clock moment), because counter 16, in which the digit code 8 will be written (1000 ) as its initial state, it will overflow and give out an overflow pulse through three clock pulses. Then, after the completion of the formation of the first NLRP and NLRPNI, the stored intermediate state of register 2 will be read from register 12 to register 2, but already as its initial phase. After that, the process of forming other NLRP and NLRPNI will begin. And if at that moment the dictionary code was not changed, then in the subsequent one out of three every intermediate state of register 2 will be stored again in register 12 and then read into register 2 as its initial phase. It is clear that, for example, the alternation order of the type “every third phase” will sort out eventually (after 12 cycles) all possible initial phases, like any other order of the type “every n-th phase”, where n = 2,3, ... , 12, and an order of the type “every 1st phase” ensures the formation of dictionaries consisting of only one specific NLRP and NLRPNI. Thus, the number n in the law “every nth phase” lays down the order of alternation of the NLRP and NLRPNI in the dictionaries, i.e. character (type) of the dictionaries NLRP and NLRPNI.

In the mode of formation of various dictionaries NLRP and NLRPNI device operates as follows.

In the 1st step, register cipher code is written in register 14 in the form of a binary code of a key digit (for example, “8” - “1000”). In the second cycle, the “Start of work” clock provides reading from the register 14 into the counter 16 digit code 8 (1000). In the 3rd step, along with the beginning of the formation of the first NLRP and NLRPNI, clock pulses from the generator 18 are received for counting to the counter 13, and through the public key 15 to the counting input of the counter 16. Since the state “8” (1000) was recorded in the counter 16 then after three clock cycles an overflow pulse will appear at its input, which will close key 15, will ensure that if the cipher code changes, write another code in register 14 to the register 14 and record the 3rd intermediate state of register 2. If the cipher code (digit code) has not changed , then the state of register 14 will not change in this cycle. After 12 clock pulses of the generator 18, an overflow pulse will appear at the output of the counter 13, which will open the key 15 and ensure that the code of the digit 8 (in this case) is read to counter 16 and the code of the filled initial phase is read into register 2. Thus, in the 14th step, the formation of the first NLRP and NLRPNI is completed and the entire device is prepared for the formation of subsequent NLRP and NLRPNI from these dictionaries, which are identified by the cipher-digit "8".

Starting from the 15th step, the formation of NLRP and NLRPN begins, determined by the initial phase 0110, which was an intermediate state of register 2 in the 5th cycle (according to Fig. 2). These NLRP and NLRPNI will have the form μ ₃ = 011011100001 and 011110100100 and thus will represent a three-character left shift of the original NLRP and NLRNI μ = {010110111000} and μ _NI = {00011110110}.

Thus, the process of forming NLRP and NLRPNI will continue according to the previously described principle so that after every 12 cycles new NLRPs shifted by 3 characters to the left will be formed. The end of the formation of dictionaries of such NLRP and NLRPNI in FIG. 2 are designated as the end of NLRP _K and NLRPNI _NIK . In the 28th measure (at the discretion of either the operator or other software), a new dictionary digit code is recorded (digit code, for example, “4-0100”). This, starting from the 31st measure, provides the formation of such dictionaries as NLRP and NLRPNI, in which each subsequent NLRP and NLRPNI will differ from previous shifts by 5 clock cycles. The process of forming NLRP and NLRPNI will be the same as previously described, except that the overflow pulse from the output of counter 16 will appear after 5 clock pulses, and as a result, the fifth intermediate state of register 2 will be stored in register 12 after the beginning of the formation of NLRP and NLRPN .

Claims (1)

A device for generating simulated non-linear non-linear recurrence sequences, comprising a shift register, the corresponding inputs of which are connected to the corresponding outputs of the control unit, an adder modulo two, the output of which is connected to the input of the shift register record, and the first adder modulo two is connected respectively to the output of the delay element, the input of which is connected to the output of the four-input first element AND, the fourth input of which is connected to the first inverse output of the shift register, the control unit, with consisting of the first and second counters, key, clock, OR element, first and second registers, where the outputs of the first register are connected to the corresponding outputs of the control unit, and the inputs from the first to fourth of the first group of the control unit are respectively connected to the inputs of the “Initial phase code »The device, and the first input of the initial phase code of the device is combined using the INSTALL OR element with the first direct output of the shift register and connected to the first information input of the first group of the control unit As a result, the second input of the initial phase code of the device is combined using the INSTALL OR element with the second direct output of the shift register and connected to the second information input of the first group of the control unit, the third input of the initial phase code of the device is combined using the INSTALL OR element with the third direct output of the shift register, the third input of the adder is modulo two and is connected to the third information input of the first group of the control unit, the fourth input of the initial phase code of the device is combined using the MOUNTING element And with the fourth direct output of the shift register, the first input of the first element And, the second input of the adder modulo two and connected to the fourth information input of the first group of the control unit, the first inverse output of the shift register is connected to the fourth input of the first element And, the first, third, fifth and the seventh outputs of the shift register are direct, and the second, fourth, sixth and eighth outputs of the shift register are the inverse outputs of the first, second, third and fourth bits, respectively, the first, third, fifth and seventh outputs the shift register is connected respectively to the first, second, third and fourth buses of the first input of the control unit, the first output of which is connected to the first clock input of the second counter and the output of the OR element, the first input of which is connected to the first information input of the key, with the first clock input and the second count input of the first counter, with the output of the pulse generator, the input of which is connected to the second input of the OR element, the second clock input of reading both memory registers, the output of the "unlocking" of the key and the start input of the control unit the third input of which is connected to the first sync inputs of recording of both registers, the third input of "locking" the key and the output of the second counter, the second counter input of which is connected to the output of the key, and the first input of which is connected to the output of the OR element, the four preset inputs of the second counter are connected respectively, with four outputs of the second memory register, four information inputs of which are connected respectively to the four buses of the fourth input of the control unit, characterized in that in the external logic unit introduced: instead of a two-input OR element, a three-input OR element is introduced and a three-input AND element is additionally introduced, and the first direct output of the shift register is connected to the first input of the second and fifth elements AND, the first input of the second OR element, the second direct output of the shift register is connected to the first input of the third element And, the third direct output of the shift register is connected to the third input of the fifth AND element, the output of which is connected to the third input of the third OR element, the fourth direct output of the shift register is connected to the second To the second inputs of the second and fourth elements AND, accordingly, the second inverse output of the shift register is connected to the third input of the first element And to the second input of the fifth element And the third inverse output of the shift register is connected to the second input of the first element And, the first input of the fourth element And, the output of which connected to the first input of the third OR element, the output of which is the output of the nonlinear recursive sequence of the device, to the second input of the second OR element, the output of which is connected to the second input of the third of the And element, the output of which is connected to the second input of the NOT element, the inverse output of the second AND element is connected to the first input of the first OR element and the second input of the NOT element, the output of which is the output of the inverted nonlinear recurrence sequence of the device.

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