RU2574805C1 - Device for generating spoofing resistant nonlinear recurrent sequences - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: method is carried out using a device for generating spoofing resistant nonlinear recurrent sequences, which comprises a shift register, a modulo two adder, a delay element, a first four-input AND element, a control unit consisting of a first counter, a switch, a clock-pulse generator, an OR element and a first register, an external logic unit, which includes a two-input AND element.

EFFECT: high noise-immunity and spoofing resistance by enabling generation of different code dictionaries of nonlinear recurrent sequences.

2 cl, 3 dwg

Description

The invention relates to techniques for generating discrete signals used in communication and radar systems with complex noise-like signals (SHPS).

The closest in technical essence to the claimed invention and adopted as a prototype is a device for forming nonlinear recurrent sequences of discrete signals (see AS 1401475 USSR, MKI GO6F 15/20. Device for forming nonlinear recurrent sequences of discrete signals [Text] / Snytkin I.I., Gorbenko I.D., Litvinenko P.T. (USSR) - 4155325 / 24-24; declared 02.12.86; publ. 07.06.88, Bull. No. 21 - 2 pp.). It contains an adder modulo two, a shift register, a delay element, the first AND element, the output of which is connected to the input of the delay element, the output of which is connected to the first information input of the adder modulo two, the output of which is connected to the input of the shift register record, the first and second direct the outputs of which are connected respectively to the second and third information outputs of the adder modulo two, a control unit, from the second to fourth AND elements and an OR element, wherein the first input of the initial phase code of the device is combined with by the power of the INSTALLING OR element with the first direct output of the shift register and connected to the first input of the second AND element and the first information input of the first group of the control unit, the second input of the initial phase code of the device is combined using the INSTALLING OR element with the second direct output of the shift register and connected to the second input the second AND element and the second information input of the first group of the control unit, the third input of the initial phase code of the device is combined using the INSTALL OR element with the third direct register output with moving and connected to the first input of the third AND element, the third information input of the first group of the control unit and the second input of the first AND element, the fourth input of the initial phase code of the device is combined using the INSTALL OR element with the fourth direct output of the shift register and connected to the first input of the first AND element and the fourth information input of the first group of the control unit, from the first to third inputs of the cipher code dictionary of the device are connected respectively to the information inputs from the first to third of the second group control lock, start input and installation input to the initial state of the device are connected respectively to the start input and to the control unit mode input, the first inverse output of the shift register is connected to the first input of the fourth element And and the third input of the first element And, the second inverse output of the shift register is connected to the second input of the fourth element And and the fourth input of the first element And, the third and fourth inverse outputs of the shift register are connected respectively to the third input of the fourth element And and the second input of the third AND element, the outputs of the AND elements from the second to the fourth are connected respectively to the first, second and third inputs of the OR element, the output of which is connected to the output of the non-linear recurrence sequence of the device, from the first to fifth outputs of the control unit are connected respectively to the synchronization outputs, to the first, second , the third and fourth information inputs of the shift register.

The control unit contains the first and second registers, the first and second counters, a key, an OR element, and a clock pulse generator, and the block mode input is combined via an INSTALL OR element with an overflow output of the first counter and connected to the recording inputs of the first and second registers and to the first control input of the key, the start input of the control unit is connected via the INSTALLING OR element with the overflow output of the second counter and connected to the read inputs of the first and second registers, to the second control input of the key, to the first input to the OR element and the start input of the clock generator, the output of which is connected to the information input of the key, to the counting input of the second counter and the second input of the OR element, the output of which is connected to the synchronization input of the first counter and the first input of the block, from the first to fourth information inputs of the first group blocks are connected, respectively, from the first to fourth to the information inputs of the first register, from the first to fourth outputs of which are connected respectively to the outputs from the second to fifth blocks, from the first to three At the same time, the information inputs of the second group of the block are connected, respectively, from the first to the third to the information inputs of the second register, the first to third outputs of which are connected, respectively, from the first to the third to the information inputs of the first counter, the counting input of which is connected to the key output.

This prototype device provides the formation of various code dictionaries of nonlinear recurrence sequences and their program change during operation with a duration of L = 8. However, this prototype device does not provide the formation of various dictionaries of nonlinear recurrence sequences and their program change during operation with a duration of L = 13. To increase the noise immunity and immunity, it is necessary to be able to form various code dictionaries of nonlinear recurrence sequences and their program change during a longer duration operation, one of these durations is the duration L = 13.

The aim of the invention is the expansion of functionality due to the formation of various dictionaries of nonlinear recurrence sequences (NLRP), providing the formation of various code dictionaries and their program change during operation of duration L = 13.

A device comprising: a shift register, the corresponding inputs of which are connected to the corresponding outputs of the control unit, an adder modulo two, the output of which is connected to an input of the shift register entry, and the first adder modulo two is connected to the output of the delay element, the input of which is connected to the four-input output the first AND element, the second input of which is connected to the third direct output of the shift register, a control unit consisting of the first counter, key, clock, an OR element, and the first register a, the outputs of which are respectively connected to the output of the control unit, and the inputs from the first to fourth of the first group of the control unit are respectively connected to the inputs of the “Initial phase code” of the device, and the first input of the initial phase code of the device is combined using the INSTALL OR element with the first direct register output shift, the second input of the adder is modulo two and is connected to the first information input of the first group of the control unit, the second input of the initial phase code of the device is combined using the INSTALL OR element with the second direct output of the shift register, the third input of the adder modulo two and connected to the second information input of the first group of the control unit, the third input of the initial phase code of the device is combined using the INSTALL OR element with the third direct output of the shift register and connected to the third information input of the first group of the control unit , the fourth input of the initial phase code of the device is combined using the INSTALL OR element with the fourth direct output of the shift register and connected to the fourth information input ne the first group of the control unit, the outputs of the AND elements from the second to the fourth are connected respectively to the first, second and third inputs of the first OR element, the output of which is connected to the output of the non-linear recurrence sequence of the device, the input “Record of the initial state” is connected to the key and the input of the first register record of the first group of the control unit, the outputs of which are connected to the inputs of the shift register, and the input "Start" is connected to the start input of the clock generator, the read input of the first register of the first group of the control unit, the key input and the first input of the OR element of the control unit, the output of which is connected to the input of the shift register record, the second input is connected to the key input, the output of the clock pulse generator is connected to the key input, counting clock inputs of the first counter, the output of which is also connected to the key input accordingly, instead of a three-input element And, a two-input element And is introduced into the external logic block, while the first input of the initial phase code of the device is connected to the fourth input of the first AND element, the second input is code and the initial phase of the device is connected to the first input of the third element And and the third input of the first element And, the third input of the code of the initial phase of the device is connected to the second input of the fourth element And and the second input of the first element And, the fourth input of the code of the initial phase of the device is connected to the second input of the third element And, the first inverse output of the shift register is connected to the first inputs of the second and fourth element And, the fourth inverse output of the shift register is connected to the first input of the first element And, the control unit instead of a three-bit register, a new four-bit register, the four inputs of which (P1, P2, P3, P4) are the inputs of the “Cipher Code”, and the read inputs are connected to the inputs “Records of the initial state” and “Getting Started”, instead of a three-digit counter, four-bit, four inputs which (P1, P2, P3, P4) are connected respectively to the outputs of the new four-bit register, the counting input is connected to the key output, and the clock input to the output of the OR element of the first group of the control unit, and the counter output is connected to the input ”, Which corresponds to the signs of“ significant differences ”and makes it possible to form various code dictionaries of nonlinear recurrence sequences and their program change during operation with a duration of L = 13.

The invention is illustrated by drawings:

In FIG. 1 shows a block diagram of a device for forming imitostable nonlinear recurrence sequences.

In FIG. 2 presents a table of the truth of the state of the device, which explains its work on the formation of one form of a nonlinear recurrence sequence of duration L = 13.

In FIG. Figure 3 shows the logical function of the device, synthesized and minimized using the Carnot map method.

Internal logic

Xb = {1011000011011}

External logic BFOP:

Optimal in its properties and characteristics of pseudo-random sequences (PSP) of duration L = 13 is the position code (µ) of quadratic residues with a two-level periodic autocorrelation function Rµ (m) = 13, m ≠ O, (mod 13), the construction of which is based on the use of the character ψ () of the multiplicative group of the field GP (p = 13).

A nonlinear recurrence sequence (NLRP) of length L = 13 has the form µ * = 1011000011011.

The use of this NLRP provides in addition to noise immunity and cryptographic stability. The possibility of using NLRP dictionaries of a given duration, built on the basis of automorphic, non-inverse-isomorphic and isomorphic transformations of the original NLRP (µ) using the program principles for changing NLRP in one dictionary, changing the NLRP dictionaries themselves, provides even greater imitability, cryptographic stability and secrecy of special communication systems.

Formation of NLRP.

At the first clock moment, the initial initial phase code for the status of the bits in register 2 is received at the device input, but the code is preliminarily written to the register 11 using the “Record the initial state” clock signal supplied to the input record of the initial state of the device and then to the input of the register 11. the second clock moment to the start input receives a pulse "Start of work", which, passing to the input of the generator 17, turns it on, and also, passing to the read input of the register 11, provides the write-off of the initial phase code from the register 11 to the register 2 and having passed through an OR gate 10 to the register write input 2, provides a record of the initial phase code in the register 2. At the same time the initial reference phase code appears at the outputs 1, 3, 5, 7, the register 2.

In the following clock periods, from the third to the fifteenth pulses from the generator 17, received at the input of the register 2 through the OR element 10, provide a sequential change in the status of the bits of the register 2 in accordance with the internal logic function so that, starting from the sixteenth cycle, the status of the bits of the register 2 are repeated. Thus, with a period of L = 13, a repetition of the register discharge states is ensured. The formation of the optimal SRP (NLRP) X _β = µ: = (10111000101) with a duration of 13 is then provided using elements 5-8.

The operation cycle can be repeated starting from the sixteenth clock moment using the “dictionary code code” supplied to the input of the device code.

Consider the mode of formation of a certain type of NLRP dictionary. The volume of the NLRP dictionary, like any other dictionary of code recurrence sequences (including LRS), is determined by the number of autoisomorphic transformations. For NLRP with L = 13 (the quadratic residue code), there are two inverse isomorphisms, the rest (18) are automorphic transformations, which are cyclic shifts of each non-inverse isomorphism. In our case, the inverse isomorphisms are NLRP = (1011000011011), the formation of which is provided by the device at the initial phase of register 2 "1011". To form other (automorphic) NLRPs, following the truth table in FIG. 2, it is sufficient to ensure the beginning of the formation of NLRP not from the initial phase “1011”, but from the initial phase such that corresponds to any intermediate state of bits in register 2 (according to the truth table, this corresponds to measures from the third to the fifteenth). The choice as the initial phase of any intermediate state of register 2 (according to the truth table) does not violate the cyclic operation (with a period L = 13) of register 2, since it does not depend on the quality (structure) of the initial phase from the volume (set) defined in the truth table initial phases (intermediate register distances 2).

The nature of the NLRP dictionary, therefore, depends on what initial phase is set in register 2 after any specific (previous) NLRPs have been formed. The order of alternation (selection) of the initial phases in this way determines the form of the generated NLRP dictionary. It can consist only of one constantly formed NLRP, only of two constantly formed NLRP, only of three NLRP, etc., and finally of twelve NLRP. Thus, in the order of alternation (selection) of the initial phases, the properties of imitation resistance, cryptographic stability of the NLRP dictionary are thus laid. The more complicated this alternation order, the higher the imitostability, cryptographic stability of the NLRP dictionary. Optimal in this sense are dictionaries constructed using such an order of alternation of NLRP, which is pseudo-random in nature. However, in any particular case determined by the operating conditions, it should be possible to change this order. These capabilities are implemented in the device by storing in the register 11 the intermediate state of register 2 in accordance with the code of the dictionary code supplied to the input of the code of the device cipher. So, for example, at the first clock moment, the code of digit 7 (1110) is entered in register 13, which means that in register 11, after the formation of the first NLRP, the third intermediate state of register 2 is remembered (in our case this will be the fifth clock moment).

The counter 15, in which the code of the digit 7 (1110) is recorded as its initial state, is overflowed and generates an overflow pulse through three clock pulses. Then, at the end of the formation of the first NLRP, the stored intermediate state of register 2 is read from register 11 again into register 2, but already as its initial phase. After this, the process of forming other NLRP begins. If at this moment you do not change the code for the dictionary cipher, then every third intermediate state of register 2 is stored in register 11 and then read into register 2 as its initial phase. For example, the order of alternation of the type “every third phase” finally sorted out (after eleven cycles) all kinds of initial phases, such as any other order “every n-th phase”, where n = 2, 3, ...., 13 , and the order of the type “every first phase” ensures the formation of dictionaries consisting of only one specific NLRP. Thus, the number in the law “every nth phase” lays down the order of alternation of the initial phases, i.e. NLRP alternations in the dictionary, i.e. character (type) of the NLRP dictionary.

In the mode of generating various NLRP dictionaries, at the first clock moment, the dictionary code is written into the register 13 in the form of a binary code of the key digit (for example, "7" - "1110"), while the key 14 is closed. At the second clock moment, the “Start of work” clock opens the key 14 and, passing to the second input of the register 13 and through the OR element 10 to the first clock input of the counter 15, provides the digit code 7 (1110) from the register 13 to the counter 15. At the third clock moment, along with the beginning of the formation of the first NLRP, the clock pulses from the output of the generator 17 go to the counter 12, and through the public key 14 to the counter input of the counter 15 and through the OR element 10 to the clock input of the counter 15. Since the state 15 is written in the counter 15 “7” (1110), then after three clock cycles an overflow pulse appears at its output, which closes the key 14, coming to the first input of the register 13, provides a code for another digit in the register 13, and arriving at the first input of the register 11, it records the third intermediate state of re istra 2. If the cipher code (code numbers) are not changed, the state of register 13 is not changed in the clock time.

After thirteen clock pulses of the generator 17 (fourteenth clock moment), an overflow pulse appears at the output of the counter 14, which opens the key 14, having come to the second input of the register 13, provides reading the code of the digit 7 in the counter 15, and also, passing to the second input of the register 11, provides reading from it to the inputs of register 2 of the code of the stored initial phase. Thus, at the fifteenth clock moment, the formation of the first NLRP ends and the device is prepared for the formation of subsequent NLRP from this dictionary, identified by the cipher - the number "7".

Starting from the sixteenth clock moment, the formation of NLRP begins, determined by the initial phase “1111”, which is an intermediate state of register 2 at the fifth clock moment. These NLRPs have the form μ ₃ = (0111011000011) and thus represent a three-character left shift of the original NLRP: μ = (1011000011011).

Thus, the process of forming NLRP continues according to the previously described principle so that every thirteen clock cycles new NLRPs are formed, shifted from the previous three characters to the left.

Claims (2)

1. A device for generating simulated non-linear non-linear recurrence sequences, comprising a shift register, the corresponding inputs of which are connected to the corresponding outputs of the control unit, an adder modulo two, the output of which is connected to the input of the shift register record, and the first adder modulo two is connected to the output of the delay element the input of which is connected to the output of the four-input first element AND, the second input of which is connected to the third direct output of the shift register, a control unit consisting of the first a counter, a key, a clock, an OR element, and a first register, the outputs of which are respectively connected to the output of the control unit, and the inputs from the first to fourth of the first group of the control unit are respectively connected to the inputs of the “Initial phase code” of the device, the first input of the initial phase code the device is combined using the MOUNTING OR element with the first direct output of the shift register, the second input of the adder modulo two and connected to the first information input of the first group of the control unit, the second input q the initial phase code of the device is combined using the INSTALL OR element with the second direct output of the shift register, the third input of the adder is modulo two and connected to the second information input of the first group of the control unit, the third input of the initial phase code of the device is combined using the INSTALL OR element with the third direct the output of the shift register and connected to the third information input of the first group of the control unit, the fourth input of the initial phase code of the device is combined using the element ORGANIZING OR with the fourth direct the output of the shift register and connected to the fourth information input of the first group of the control unit, the outputs of the AND elements from the second to the fourth are connected respectively to the first, second and third inputs of the first OR element, the output of which is connected to the output of the nonlinear recurrence sequence of the device, from the first to fifth outputs the control unit is connected respectively to the synchronization outputs, to the first, second, third and fourth information inputs of the shift register, characterized in that in the external log block instead of a three-input element And a two-input element And is introduced, while the first input of the initial phase code of the device is connected to the fourth input of the first And element, the second input of the initial phase code of the device is connected to the first input of the third And element and the third input of the first And element, the third input of the initial code the phase of the device is connected to the second input of the fourth element And and the second input of the first element And, the fourth input of the code of the initial phase of the device is connected to the second input of the third element And, the first inverse output reg the shift unit is connected to the first inputs of the second and fourth element And, the fourth inverse output of the shift register is connected to the first input of the first element And, the outputs of the elements And from the second to fourth are connected respectively to the first, second and third inputs of the first element OR, the output of which is connected to the output nonlinear recursive device sequence. 2. The device according to claim 1, characterized in that the control unit includes a second four-bit register, a second counter with four inputs, and it also contains a first register, a first counter, a key, an OR element, and a clock generator, wherein the block mode input is combined through the INSTALLING OR element with the overflow output of the first counter and connected to the recording outputs of the first and second registers and to the first control key input, the start-up input of the control unit is combined via the INSTALLING OR element with the overflow output of the second counter it is connected to the readout outputs of the first and second registers, to the second control input of the key, to the first input of the OR element and to the start input of the clock generator, the output of which is connected to the information input of the key, to the counting input of the second counter and to the second input of the OR element, the output of which is connected to the synchronization input of the first counter and to the first input of the block, from the first to fourth information inputs of the first group of the block are connected, respectively, from the first to fourth to the information inputs of the first register a, from the first to fourth outputs of which are connected respectively to the outputs from the second to fifth blocks, from the first to fourth information inputs of the second group of the block are connected, respectively, from the first to fourth information inputs of the second register, the first to fourth outputs of which are connected respectively from the first to fourth to the information inputs of the first counter, the counting input of which is connected to the key output.

Images