SU1439751A1 - Binary to fibonacci code converter - Google Patents

Abstract

The invention relates to computing and can be used in systems for converting information represented by a two-way code into a Fibonacci code. The aim of the invention is to increase the speed of the converter. The converter contains input register 1, adder 2, blocks 3-5 of the permanent memory, output register 6, delay element 7, information and control inputs 8 and 9, outputs 10 of the converter. I il.

Description

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The invention is related to computing, and will be used to convert information represented by a binary code into a Fibonacci code,

The purpose of the invention is to increase the speed of the converter.

Pa drawing presents the functional diagram of the Converter.

The converter contains the input register 1, the adder 2, the blocks 3-5 of the permanent memory, the output register 6, the element 7 C-supports, the information control inputs 8 and 9 and the outputs 10 of the converter.

The converter works as follows

When applying, to the control input 9 of the resistive signal, the input code is written to input register 1, the information contained in the lower m bits of the input code comes from the corresponding outputs of input register 1 to the first inputs of the adder 2, depending on the size n input code parameter m selects-1 with equal,. when n is odd.

p-2 and

when n is even.

The information contained in the higher bits of the input code is fed to the inputs of the first 3 and second 4 blocks of permanent memory. Permanent memory unit 3 is encoded in such a way that when the value of the leading bits of the input code is fed to its input, the code from the conversion of this information into the Fibonacci code contained in the 1 lower bits of the Fibonacci code is generated in binary form. the value of parameter 1 is selected from the condition Cf (l-3) 7/2 -2. The residual code from the output of block 3 of the permanent memory goes to the second inputs of adder 2, the output of which forms the code of the sum of the residual and the input value contained in m lower-order bits dah input code. The code from the output of the adder 2 is fed to the inputs of the third block 5 of the permanent memory. Block 5 is encoded in such a way that when a binary code is fed to its input with a digit {log-1 (1 + 1) +1, its output is formed

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five

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Fibonacci code 1 low-order output code.

Constant memory unit 4 is encoded in such a way that when information supplied to its inputs contained in the nm group of the higher bits of the input code, the Fibonacci code values in the older bits group start at the output of the (1 + 1) th ,

After the transient time in the adder 2 and blocks 3-5, the control signal from the output of the delay element 7 is sent to the control input of register 6, as a result of which the information from the outputs of blocks 4 and 5 of the permanent memory is written to the output register.

Image form

The binary code to Fibonacci code converter containing the p-bit (p-bit input code) input register, the information and control inputs of which are respectively the information and control inputs of the converter, the adder and the output register, characterized in that In order to increase the speed of the converter, the blocks of the permanent memory and the delay element, the input of which is connected to the control input of the converter, are entered into it, and the output is connected to the control input of the output register, outputs m small nsh and n-m. Senior bits of the input register p-1n-2

five

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t -j-

(m - g - with n - odd,

when n is even) are connected respectively to the first inputs of the adder and the inputs of the first and second blocks of permanent memory, the outputs of the first block of permanent memory are connected to the second inputs of the adder, whose codes are connected to the inputs of the third block of permanent memory, the outputs of which are connected with inputs 1 lower bits of the output register (where 1 is determined from the ratio (/ (l-S) 7 / / 2 -2, if / i) is the weight of the i-th bit of the Fibonacci code), the output of the second block of the permanent memory This is connected to the inputs of the higher bits of the output register, the outputs of which L are output transducer,

Claims (2)

Form Ula Images Converter of binary code to Fibonacci code, containing p-bit (η-bit input code) input register, information and control inputs of which are respectively information and control inputs of the converter, an adder and an output register, characterized in that, in order to increase the speed of the converter , blocks of read-only memory and a delay element are introduced into it, the input of which is connected to the control input of the converter, and the output is connected to the control input of the output register, outputs m are younger and nm. of the older bits of the input register, η-l p-2 (m = at n is odd, m = at η is even) are connected respectively to the first inputs of the adder and the inputs of the first and second blocks of read-only memory, the outputs of the first block of read-only memory are connected with the second inputs of the adder, the outputs of which are connected to the inputs of the third block of read-only memory, the outputs of which are connected to the inputs of the lower 1 bits of the output register (where 1 is determined from the relation 7 (1-3) b> 2 -2, V / i) - the weight of the i-ro code bit Fibonacci), the output of the second block of read-only memory is connected to the inputs of the upper bits of the output register, the outputs of which are the outputs of the converter.