SU1434547A1 - Device for converting pulse-code signals into delta-sigma modulated signals - Google Patents

Abstract

The invention relates to computing and communication technology, its use in information transmission systems allows for improved conversion accuracy. ycji-poftcTBO contains adder 1, the elements are NOT 2, 3. and the buffer register 4. By introducing the BANKS 5-7, element AND 8, element OR 9, equivalence element 10, and signal strength switch 11, the device provides more accurate error signal coding at the same speed. 1 il. c (o

Description

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The invention relates to computing and communication technology and can be used in information transmission systems.

The purpose of the invention is to improve the accuracy of the conversion.

The drawing shows the functional | on the scheme of the proposed device. I The device contains an adder 1, the first 2 and the second 3 elements are NOT, the buffer register 4, the first 5, the second 6 and the third 7 BAN elements, the P 8 element, the OR 9 element, the equivalence element 10, the level switch | signal, information. inputs 12, | clock input 13 and output 14.: The device operates as follows.

j The PCM signal (pulse pulse modulation signal) signal is received. | to inputs 13, the bit is equal to n | whereby the sign (most significant) bit from the head when fed to the adder 1 is inverted by the HE element 2. I Operation the device is described by

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the signals at the outputs of the adder 1, respectively, at times t and t-1, which are counts of the error signal DSM (delta-sigma modulation)) signal at the output 14 of the device, which is also a signal in the feedback circuit DSM input signal.

Let the input signal have n-1 bits, including signs, and X | 1, Inverting the sign bit with the first element NOT 2 means converting a signal into a direct code. The range of change of the error signal according to (1) is divided into three levels, i.e. O e tt, 1.5; 1.5 e 2.5 and, 5, which leads to more than 50

From tab. 1 it follows that the difference tT, - (Chup can be obtained by dropping the (n - "- 1) -th bit of the signal at the outputs of register 4, saving (n-1) .th digit and inverting the n-th bit for the fourth and the fifth

error signal coding, box. Thus, it is required that the DSM is integrated into the DSM is the integrated value of the difference signal, input X, Then

signal X and approximating

signal q.

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out, analyzing the three major bits of e ,. for combinations of values presented in the fourth and fifth columns of the table. 1, invert 9 S i-

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1.5 6 e "., 2.5 O 6 .e"., 1.5

(2)

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Thus, if the range of the error signal is divided into three subbands, then the approximating signal q should take three values, which can be encoded with at least two bits, and not one, as in the prototype. On the other hand, it is desirable that the speed of the device changed slightly, i.e. it is necessary not to introduce a significant delay into the feedback circuit, namely from the output of the register 4 to the second inputs of the adder 1. We will compose the table. 1 of all possible values of signals on .n + and th, nth and (n-1) th outputs of adder 1, taking into account the fact that 3Tit bits have weights equal to 2, 1 and 0.5 at ( x | 1, In this table, based on (2) we write the value of q

fv

and the values of the first three digits of the difference e, - q, taking into account the same weights.

From tab. 1 it follows that the difference tT, - (Chup can be obtained by dropping the (n - "- 1) -th bit of the signal at the outputs of register 4, saving (n-1) .th digit and inverting the n-th bit for the fourth and the fifth

out, analyzing the three major bits of e ,. for combinations of values presented in the fourth and fifth columns of the table. 1, invert the value of the n-th bit, and in all other cases leave the value of the n-th bit unchanged, and secondly, it is necessary to generate control signals for the switch 11, at the output of which a three-level signal with a DSM is generated, depending on q values. Based on the table. 1 easy to make a table. 2 required switchings.

table 2

In this case, it is considered that the control signals at the inputs of the switch 11 are coded for different values of q, as shown in Table. 3.,

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Table 3 Entry 1

Entry 2

As a signal level switch 11, you can use any circuit that has three output levels (for example, you can use logic elements that are included in the chip

K155LP8 pa with three output states, connecting to its output a chain of two identical resistors connected in series, one end of which is connected to the common bus and the other to the power supply).

It should be noted that the speed of the device is estimated as follows:

f (. s ,,.

where t, g is the delay time of the logical

block 6.

It can be seen from the drawing that С, where the delay time of one logical element. Insofar as,. by volume

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The properties are almost unchanged.

Thus, due to a more accurate error signal coding, the accuracy of converting the I1Sh signal to the signal with a DSM is increased.

Claims (1)

Formula Eteni A device for converting signals with pulse-code modulation into signals with delta-sigma modulation containing an adder, the inputs of the first (n-1) -th bits of the first group of inputs of which (n is the width of the input signal), and the input The n-th bit of the first group of inputs is not connected to the corresponding information inputs of the device through the primary input element, the outputs of the adder are connected to the single-input information inputs of the buffer register, the outputs of the first - (nl) -ro bits of which are connected to the inputs of the same name the second group of inputs of the adder, the output of the (n + 1) -th bit of the buffer register is connected directly and through the second element is NOT to the inputs of the (n + 1) th bits of the second and first groups of inputs of the adder, the clock input of the buffer register is a clock input of the device, which is different from the fact that, in order to improve the accuracy of the conversion, a signal level switch, an element IL1-1, an equivalence element, an AND element and BAN elements, the first prohibiting input of the first and the first permitting input of the second rec elements PET merged and connected to 5 14345476 in | output (nl) -ro bit buffer buffer AND and prohibiting input of the third rJHCTpa, output of the n-th bit of which element BAN, the second input is combined with the first input of the element AND, permitting inputs of the first E | equivalence, the second prohibition of the third and the prohibiting entrance of the second one of the first and second permitting elements of the BANKS are combined and the input of the second BANNER elements are turned off to the output of the (n + 1) -th bit of the boat which are connected to the elec- tron inputs register, the output of the element AND and CENT OR, whose output is connected inverse move the third element of the second input of Q element equivalent inverted respectively connected to Yusti, the output of which is connected kpervym and second inputs of switch 1HODU nth discharge gruppyurovn second signal which is vschrd - combiner passages, a first input element, an output of the apparatus.