SU369702A1 - ANALOG-DIGITAL CONVERTER - Google Patents

Description

one

The invention relates to computing and can be used in the recording equipment of the three automation of research of various processes.

The analog-digital P is known (a converter containing a B of each discharge unified element, a current transducer into voltage, a trigger, two AND circuits, whose inputs are connected to the discharge trigger outputs, and the outputs are connected to one input of the OR of the following bits two additional circuits “And, one of the inputs of which are connected to the outputs of the trigger bits.

However, the known transformer has insufficient speed and a large conversion error, since about half of the conversion error falls on the dynamic error, the value of which is different for even and odd quantization levels.

In order to increase speed, reduce 1 error and eliminate reading errors in (the proposed analog-digital converter in each bit, except the senior one, another input of the first OR circuit and the first AND circuit of the second circuit is connected to the output of the unified element OR and the second circuit "AND through the circuit" NOT, the other inputs of the additional circuits "And through the block forming the readout signal are connected to the outputs of the low-order trigger.

FIG. 1 is a block diagram of the proposed digitizer with five binary bits; in fig. 2 scheme of the unified element.

The proposed converter contains current to voltage converters 1–4, unified elements 5–9, triggers 10–

14, bus 15 of installation “O, circuits“ AND 16-18, circuits “AND 19-21, delay line 22, circuits“ NOT 23-27, circuits “OR 28-35, read buses 36-45, circuits“ AND 46 -55, read signal driver 56, current switch transistors 57 and 55, transistor 59 and 60 zmitter repeaters, resistors 61 and 62 emitter repeaters, diodes 63 and 64, resistors 65 and 65, transistors 67-69, resistors 70 and 71, capacitor 72.

Speed converter

t / Bx input signal (), e exceeding

The weights of the lower bit hu during the transitional processes in one conversion cycle,

works as follows.

In the initial state with i / Bx (W

owl currents on converters / -4 current

no voltage is applied, while the level

the reference voltages of the unified elements 5–9, at the outputs of which 1 the signal “O, corresponding to the fl.

Triggers 10-14 are set to IB status “About input setting“ About signal from bus 15. Signal “1 propagates in the least significant bit of circuit“ AND 16-IS, prepared by one Input signal from the outputs of the corresponding three years 11 -13. The propagation of the signal "About IB junior bits is prohibited by applying a signal to one of the inputs of the circuits" And 19-21 from the corresponding outputs of the flip-flops 11-13.

The characteristic quantum signal equations (UHBCO IB conversion process are

in hu2a and f / Bx / g „(2а + 1), where a О, 1, 2 .... (2« -1-1).

For f / Bx / gi (2a-J-1), the equalities i / et and Ivk are fixed in the unified element (n - t) of the discharge.

The state of the trigger in this md will change from "O to" 1 at the end of the transient processes successively in the corresponding delay lines, the unified element, the OR scheme and the trigger.

At t / Bx 2ahu, the equality is fixed in the unified element (n - r). A discharge in which at the end of the transition processes a weight current 1 (n - r) is formed, changing the level of the reference voltage in parallel in all the least significant bits . The sign of the increment of the reference voltage level is determined by the sign of the derivative of the input signal. At the same time, the signal from the outputs of the unified elements is fed to the "NOT," AND and "OR circuits for generating codes in triggers 10-14. The processes of code formation in the younger ones by the significance of the bits proceed in parallel and not aaiBHCHMO one from another.

The discrepancy between the reference voltage level and the input signal in the lower bits is fixed by the unified elements in the corresponding bits.

At the end of the transient processes, weight currents are formed, which change the level of the reference voltage simultaneously on all subsequent bits by the value of the corresponding weight. The increment sign of the reference voltage is opposite to the sign of the derivative of the input signal. From the outputs of the unified elements 5–9, the signal arrives at the circuits “NOT 25–27, the circuits“ OR.2§- 35, which cause | secondary (false) code generation by triggers 10–14.

The duration of the sequential establishment of transients IB transducer x / -4 and elements 5-9 does not depend on the number of bits.

The process of forming a code with triggers 10-14 with increasing proceeds as follows.

As a result of the conversion to the pre-existing quantization levels, the trigger in (n - t) bit is in the state

and in the 1G1 coded bits-IB state of the signal.m. from the trigger output (n - d) one of the “And this bit” schemes was prepared, and the other was closed with a signal from this

trigger These schemes change their state only under the action of a signal corresponding to "I from the output of the unified element or from the output of the corresponding scheme to" NOT.

As a result, if the input signal exceeds the reference voltage level in (l - d), the discharge signal "1 s. The output of the unified element passes through the corresponding circuit" And then through one of the circuits

“OR 32-35 (corresponding to this bit) affects the inputs of the corresponding triggers in subsequent bits and translates them to the state“ O. At the same time, the signal from the output of the unified element of the corresponding bit passes through another scheme “OR of this bit and affects the input of the corresponding trigger a. When the input signal decreases

code generation is similar.

To read the code generated by the 10–14 IB trigger of the 36–45 bus number, each time a signal from the trigger output is fed to one of the inputs of the AND

46-55 readings (in the corresponding bit), to another input of these circuits a read signal is generated, formed in the read signal shaper 56 when the signal at the trigger outputs changes to (l - i) bit.

The unified element (Fig. 2) is two current switches that are connected paraphase. The first current switch is made on transistors 57

and 55. Transistors 59, 60 with resistors 61 and 62 form emitter repeaters, from which an input signal is fed through the left (UHV and a reference signal through the right. Diodes 63 and 64 in the collector circuit of the current-switching transistors serve to increase the sensitivity. Output The first switch of the current switch from resistors 65 and 66 goes to the bases of transistors 67 and 68 of the second switch of current.

69 with a resistor 70 serves to create a discharge discharge current. The circuit from resistor 71 and capacitor 72 is turned on to increase the sensitivity at the input.

Subject invention

An analog-to-digital converter containing in each discharge a unified element, a current-voltage converter.

a trigger, two AND circuits whose inputs (connected to the outputs of the trigger trigger, and outputs connected to one inputs of the OR of the following bits, two additional AND circuits, one of which inputs connected to the outputs of the trigger bits that differ

T6i, that, with the purpose of improving the response, reducing the conversion error and the error reading error, in each bit, the most senior, another input of the first P1LI circuit and the first circuit is connected to the output of the unified element

"And the other and the other input of the second circuit" OR and the second circuit "And through the circuit" NOT, the other inputs of the additional circuits "And through the read signal generation unit are connected to the low-level trigger outputs.

FIG. one