SU1737726A1 - Device for transforming discrete information - Google Patents

Abstract

Usage: refers to automation and computing and can be used in the implementation of various devices for converting discrete information. The essence of the invention: the device contains m input terminals xiXm /, m inverters 1i 1m /. gated MOS transistors 2i, ... 2m /, n - channel MOS transistors 3i, .., 3m /, m weighing resistors 4i4m and 5i, .., 5m, which are provided for removing from mid-points 6i ,. ., 6m voltages proportional to the weighted values of the input signals D-flip-flop 8. 1 Il. CO with VI with XI xi about

Description

The invention relates to automation and computer technology and can be used in the implementation of various devices for converting discrete information, in particular, to create analogs of neural networks based on LSIs with complementary MOS transistors (CMOS transistors).

Known devices of this type, made, in particular, on standard threshold (logical) CMOS circuits. The known devices are characterized by compactness, speed and low power consumption, however, their structure is adapted for converting and translating analog information, which limits their use.

Also known are devices that simulate (imitate) the work of neurons.

The disadvantages of the known devices are the analog nature of the information to be converted, as well as the complexity and multi-elementity of the circuit, combined with increased power consumption. In both cases, the advantages of modern CMOS technology are not used.

The closest to the present invention is a device for converting discrete information containing at least one input terminal connected in series between a power bus and a common bus, a first MOS transistor, a voltage divider, whose midpoint is connected to the output of the device through a threshold memory element, the second MOSFET, the gate of one of the MOSFETs is connected to the input ter / inal.

The known device can be used to convert the input discrete information from one or more terminals in order to store it later or transfer it to networks of computing facilities. The known device has all the main advantages of MOS circuits, has low power consumption and good integrability in LSI. The input (information) MOS transistors of the known device are made with a single-type channel conductivity (n-channel or p-channel) and with different parameters (length and width) of the gate. Similarly, the transistors of the voltage control unit are reduced from the midpoint of the pitch circuit.

The drawbacks of the device are the increased sensitivity to the input signal level and the relative instability of the output voltage, as well as the complexity of the practical provision of a given information weight of the input signal in the process of learning a formal neuron, made according to this scheme. These flaws can be even stronger.

to develop when creating devices with a large number of inputs, the weights of which differ significantly.

The aim of the invention is to increase the stability of the perception and transformation of information, and also to simplify the configuration of the specified functional characteristics of the device,

This goal is achieved by the fact that in a device for converting discrete

5 information MOS transistors are made of different channels, the gate of one of them is connected to the input terminal through an inverter, the voltage divider is made on the weight resistors, and a resistor is turned on between the common width and the midpoint of the voltage divider.

The invention consists in combining CMOS circuits with a voltage divider on the weight resistors and an inverter,

5 which can also be made on the basis of CMOS transistors. This ensures that when the transistors are of different channels, the circuit is very bistable and the output voltage remains constant from the midpoint of the unit even if the input signal level deviates from the specified and inaccurate implementation of the gate parameters.

In addition, the proposed device contains a resistor connected between the common bus and the midpoint of the voltage divider. In combination with the weight resistors, this simplifies the circuit of the device and facilitates its adjustment.

0 At the same time, the device contains at least two input terminals and the corresponding number of MOS transistors and voltage dividers, the midpoints of which are connected to the input of the threshold retaining element.

The preferred option is to use as a threshold storage element a known D-flip-flop scheme, which allows the most natural recording of the signal level from the midpoint of the divider (weighted sum of these signals). It is also possible to use other types of threshold elements, in particular the RS flip-flop.

5 The drawing shows the scheme of the proposed device.

A device with m input terminals Xi, ... Xm (m 1) contains inverters 1i, ..., 1m, p-channel MOS transistors 2i, ... 2m. n-channel MOS transistors 3i3m. weight resistors 4i, ..., 4m and 5t5m, form

m voltage dividers, midpoints 6i, ..., 6m of which are connected to input 7 of D-flip-flop 8. The device is powered by bus 9 and common bus 10 with resistor 11. O (and 5) flip-flop (outputs) 8 is the output of the entire device.

The device works as follows.

In the absence of signals at the inputs: XGO (HI, t) all pairs of MOS transistors 2i and 3 | closed and the signal at the input of the 7 D-flip-flop 8 is also zero. If at least some of the inputs have a signal (k-1.1: I t), then the corresponding n-channel and p-channel transistors (GC and 2K) are unlocked and a voltage is generated at the input 7 of the D-flip-flop 8 corresponding to the weighted values of the input signals with weight at c. Weights are provided with an appropriate setting (selection of values) of resistors 4 and 5k and resistor 11. The total weighted signal at the input is 7 6-trigi repa8: Y yk.

k 1

If the level Y is below a predetermined trigger threshold, this signal is not perceived (fixed as O). Otherwise, the trigger is activated and remembers the signal Y, qualifying it as 1.

The operation of the proposed device can be considered as an analogue of the functioning of a formal neuron sensitive to a certain level of excitation, including complex, with a multi-bit binary input.

The technical and economic advantages of the proposed device lies in the simplicity of its implementation — based on the known elements of microelectronics and the developed manufacturing techniques.

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CMOS circuits (as part of NS and LSI) and a wide range of applications, including in artificial intelligence systems.

In addition, the design of the device is sufficiently flexible with respect to possible modifications of its basic elements and connections.

Claims (3)

Claim 1. Device for converting discrete information, containing at least one input terminal connected in series between the power bus and the common bus, the first MOS transistor, voltage divider, the midpoint of which is connected to the output of the device through the threshold memory element A transistor, a gate of one of the MOS transistors, is connected to an input terminal, characterized in that, in order to increase the perception stability and information conversion, as well as to simplify Data functional device characteristics of MOS transistors formed raznokanalnymi, wherein the gate of another PMOS-transistor is connected to the input terminal through an inverter, a voltage divider is formed on weighted resistors, and voltage divider resistor is included between the common bus and the midpoint. 2. The device according to claim 1, which is distinguished by the fact that it contains at least two input terminals and the number of MOS transistors and voltage dividers corresponding to their number, whose midpoints are connected to the input of the threshold storage element. 3. The device according to claims 1 or 2, characterized in that the threshold storage element is designed as a D-flip-flop.