SU1191909A1 - Pipeline device for taking antilogarithms of binary number arrays - Google Patents

Abstract

A CONVEYOR DEVICE FOR POTENTIALING BINARY NUMBER MASSIFES containing the input order register, the input mantissa register, the output order register, the output mantissa register, two adders, the first memory block, and the input of the device's mantissa connected to the information input of the mantissa register, and the first memory block, the input of the device mantissa connected to the information input of the mantissa register, and the first memory block, the input of the device's mantissa connected to the information input of the mantissa register, and the first memory block, the input mantissa of the device is connected to the information input of the mantissa register, and the first memory block is connected to the information input of the mantissa register. This is because, in order to improve speed, eight registers, a shift block, a second memory block, a third adder, a quad, a switch, a synchronization block, and a NOT element are entered into it, and the order of the device is The device is connected to the information input of the input order register, the output of which is connected to the control input of the shift unit, the information inputs of which are connected to the outputs (n-1) of the lower bits of the input mantissa register (where n is the number of bits of the input mantissa register), the output of the first bit of which is connected to the information inputs of the first bits of the first and second registers, the information outputs of the shift unit are connected to the information inputs (n-1) of the least significant bits of the next register, the outputs of which bits are connected Inen with address inputs of the first memory block (where K is the number of high bits of the second register), the output of the first memory block is connected to the first input of the first adder, the second input of which is connected to the output of the second register, codes (fl) of lower bits the shift is connected to the information inputs (-1) of the lower bits of the first register (where is the number of the higher bits of the shift block), the output of the first register (L register is connected to the information input of the third register, the output of the first. the adder is connected to the information input of the fourth register, the outputs of the bits of the second register are connected to the information inputs of the fifth register, the output of the third register is connected to the information input of the sixth register, the output of the fourth register of that register is connected to the input of the quadrant, the output of which is connected to the information input the seventh register, the output of the first register is connected to the informational input of the eighth register, the output of which is connected to the address input of the second memory block, the output of the sixth register ene to a first input of the second adder significant bit of the second input through which the element is not connected to the output of the first discharge eighth register, the seventh register output connected to the input of the first group with a shift on

Description

one bit in the direction of the lower bits of the third adder, and the group of inputs is connected to the outputs of the second memory block, the output of the first bit of the eighth register is connected to the control input of the switch, the first group of information inputs is connected to the output of the third adder, whose outputs connected to the information inputs of the second group with a shift of one bit in the direction of the lower bits of the switch, the output of which is connected to the information input of the output mantissa register, the output of which is connected The output of the mantissa of the device, the output of the second adder is connected to the information input of the output register {and the order whose output is connected to the output of the order of the device, the first input of the synchronization unit is connected to the start input of the device, the second input of the syncro unit. connected to the reset input of the device, the first output of the synchronization unit mode is connected to the readout output of the device, the first sync output of the sync block of the connection with sync inputs of the order and mantissa input registers, the second sync output of the synchronization unit of the first and second sync inputs the sync pulses of the synchronization unit are connected to the synchronous inputs of the third, fourth and fifth registers; the fourth output of the sync pulses of the synchronization unit is connected to the sync input The sixth, seventh, and eighth registers, the fifth sync pulse output of the sync block is connected to the sync inputs of the output order and mantissa registers, the second sync pulse output of the sync block is connected to the sync inputs. the first and second registers, the third output, the sync pulses of the synchronization unit are connected to the synchronous inputs of the third, fourth and fifth registers; the fourth sync output of the synchronization unit is connected to the sixth, seventh and eighth synchronization inputs; and mantissa, the second output of the mode of the synchronization unit is connected to the output of the recording device.

one

The invention relates to computing and is intended for use in universal and specialized computing devices when processing large data arrays, in a floating point format.

The purpose of the invention is to increase the speed of action.

FIG. 1 is a functional diagram of a device for potentiating binary number arrays; in fig. 2 - synchronization unit; in fig. 3 - timing charts of the device.

; The device for potentiating the arrays of binary numbers contains the input register of the order 1, the input register of the mantissa 2, the shift block 3. The first and second registers 4 and 5, the first memory block 6, the first adder

7, third, fourth and fifth registers 8, 9 and 10, quad 11, sixth, seventh and eighth registers 12, 13 and 14, the second memory block 15, the evil NOT 16, the second and third adders 17 and 18, the switch 19, the output register is about 20, the output register of the mantissa 21, the synchronization unit. 22 with inputs 23 and 24 and output

10 mi 25-31. Sync block 22

(Fig. 2) contains a pulse generator 32, an AND element 33, a trigger 34 and a shift register 35, with the direct output of the pulse generator 32 connecting

15 is not with a gate input of the trigger 34, and an inverse output with a gate input of the shift register 35. The input Reset 24 is connected to the reset inputs of the trigger 34 and the shift

20 register 35. Input Start 23 is connected to the first input of an AND element 33, the second input of which is connected to the inverted output of the trigger 34, and the output of the AND element 33 is connected to the information input of the trigger 34, the direct output of which is connected to the information input of the shift register 35. The output of the first digit of the shift register 35 is connected to the output 25. Reading of the synchronization unit 22, the output of the third discharge - with the output 26, the output of the fifth discharge with the output 27, the output of the seventh discharge - with the output 28, the output of the ninth digit - with exit 29, exit of the eleventh bit - with the output 30, the output of the thirteenth bit — with the output 31 of the synchronization block 22, the first output 26 of the synchronization block 22 is connected to the outlets of the order and mantissa I and 2 output registers, the second exit 27 is connected to the synchronous inputs of the first and second registers 4 and 5, the third and fourth output 28 - with the synchronous inputs of the third, fourth and fifth registers 8, 9 and 10, the fourth output 29 with the synchronous inputs of the sixth, seventh and eighth registers 12, 13 and 14, the first output OUTPUT 30 - with the synchronous inputs of the output registers of the order and mantissas 20 and 21. The outputs of the input register are about 1 connected The control inputs of the shift unit 3, whose information inputs are connected to the outputs of all bits of the input register of the mantissa 2, excluding the first (sign). Output

the first bit of the input register of the mantissa 2 is connected to the inputs of the first bits of the first and second registers 4 and 5, the inputs of the remaining bits of which are connected to the outputs of the block before the shift 3. The outputs of the second register 5 are connected to the first inputs of the first adder 7, the second inputs of which are connected the outputs of the first memory block 6. In addition, the outputs K of the older 45 bits of the second register 5 are connected to the address inputs of the first block, 6, and the inputs of the fifth register, 10. The outputs of the first adder 7 are connected to the inputs of the fourth register 50 9. Outputs , the fourth register 9 is connected to the inputs of the quad 11, the outputs of which are connected to the inputs of the seventh register 13. The second register of the fifth register 10 is connected to the inputs of the eighth 55 register 14. The outputs of the eighth register 14 are connected to the address .. The inputs of the second memory block 15.

intermediate computing and to provide a pipelined processing method. Registers 5, 9, and 13 are of size n, registers of 4, 8, and 12 are of I, and registers of 10 and 14 are of K, while K is determined from approximation conditions.

The calculation of the function y 2 of the argument X (| x1 2.) is performed as follows.

In floating point form, X is represented as

2

X 2;

where z is the argument mantissa (0.5 i

z, kl);

Zj is the order of the argument (). Denormalize the argument, i.e. we represent it as the integer and fractional part

 In addition, the output of the first bit of the eighth register 14 is connected to the input of the NOT element 16 and the control input of the switch 19. The outputs of the second memory block 15 are connected to the second inputs of the third adder 18, the first inputs of which are connected to the outputs of the seventh register 13 with a shift one bit to the left. The outputs of the third adder 18 are connected to the first inputs of the switch 19 with a shift of one bit to the right. The second inputs of the switch 19 are connected to the outputs of the third adder 8 without shifting. Switch outputs are connected to. inputs of the output register of the mantissa 21. The output of the element NOT 16 is connected to the second input of the lower bit of the second adder 17. The second inputs of the second inputs of the remaining bits of the second adder 17 are fed. O. The first inputs of the second adder 17 are connected through the sixth and third registers 12 and 8 to the outputs The first register 4, the outputs of the second adder 17 are connected to the inputs of the output register on the order of 20. The switch can be selected by anyone with sufficient speed. The shift block is easy to build with the help of selectors-multiplexers. The principle of building a high-speed shifter is well known. The first-eighth registers 4, 5, 8, 9, 10, 12.13 and 14 are intended for short-term memorization of the result, where z, is the whole part of the argument (Uj | c2); 84 fractional part of the argument (. Note that the sign of Zj and z is determined by the sign of the mantissa of the argument. We calculate the function y 2 as follows: With a positive argument x, the value of z is also positive and the expression holds. With a negative argument x 0,5i (z O) Therefore, for a negative argument, the value 2 represents the output number mantissa, and the values z is an order. With a positive argument, the value can be normalized by shifting one bit to the right, in which case the output number mantissa is 0.52 - Zj + The argument is renormalized by: shift block 3. 2 (The calculation of the function y is based on the segmented approximation method by the expression y, A 0.5 (x + B), where the constants A and B are chosen from the condition of minimizing the absolute error. The range of variation of the argument (- 1 -Z ii) is divided into intervals, the number of which is determined by the required accuracy, and the boundaries of the intervals are expressed by the highest order of rows of the argument. At different intervals, the constants A and B have different meanings. The B constants are stored in the first memory block 6, and the Co-Aants are stored in the second memory block 15. Addressing each memory block is performed by the K bits of the argument, which determine which interval the argument is in . The device works as follows. Before the device starts to operate, the Reset 24 signal (Fig. 3a) trigger 34 and the shift register 35 of the synchronization unit 22 are reset. On the Start 23 signal (Fig. 36), the And 33 element transmits the signal from the inverse output of the trigger 34 to the information input of the same trigger. The trigger 34 operates in the mode of dividing the frequency of the pulse generator 32 (Fig. 3c) into two (Fig. 3g). On the falling edge of the signal of the pulse generator 32, the information from the output of the trigger 34 is entered into the shift register 35. As a result of the operation of the device at the outputs 25-31 of the synchronization unit 22, a ladder of control pulses of the internal registers of the device and the ext. these are memory circuits. In this case, the output 25 Read (Fig. 3 d) is used to control the reading of the next data word from the external memory, the output 26 (Fig. 3 e) - to control the drift of numbers in registers 1 and 2, the output 27 (Fig. 3 k) - to registers 4 and 5, exit 28 (Fig. 3 l) - to registers 8-10, exit 29 (Fig. 3 m) - to registers 12-14, exit 30 (fig. 3 n) to registers 20 and 21 , output 31 (FIG. 3 o) is for controlling the recording of the result in an external memory. After the removal of the start 23 signal, the synchronization unit 22 stops generating control signals starting from the upper stages of the conveyor. This ensures that the processing of operands in the internal registers of the device during the pick-up of Start 23 signal is correctly completed. In the first operation cycle of the device, register 1 receives the order of the argument k, and register 2 receives the mantissa. From the output of register 1, the value of the order of the argument goes to the control inputs of the shift block 3. In this case, the first (sign) bit indicates the direction of the shift (1 - right shift, O - left shift), and the number determined by bit 2-t register 1, - on the number of shifts. The significant bits of the mantissa register 2 (2-p) are fed to the information inputs of the shift block 3, where the Denormalization of argument x is produced. In the second measure, the sign value of the argument x. written into the first (sign) bits of registers 4 and 5, into bits 2 - G of register 4 the whole part of the argument x is written, and in bits 2 - n of the register 5 - fractional 7 part of the argument x. Registers 1 and 2 record the order and mantissa values of the new argument x. From the output of register 5, the value of the fractional part of the argument x is fed to the adder 7, at the same time from the memory block 6 at the address specified by the most significant bits of the fractional part of the argument X, the constant B is selected and also fed to the adder 7, In the adder 7, the sum zv is produced + + RF In the third cycle, the value of + B is written into register 9 and squared in square 11. At the same time, the value of K of the most significant bits of the fractional part of the argument x is written into register 10, and the entire part of the argument X from register 4 is rewritten from into register 8 In that At the time of the registers and 2, the order and the time of the new number Xj are entered, and registers 4 and 5 are integral and fractional parts of the number x / I. In the fourth cycle, the value (z + + VO is written to register 13 and shifted one bit to the right goes to the adder 18. At the same time, the value K of the most significant bits of the argument x from register 10 is rewritten into register 14 and fed to the address inputs of memory block 15, from where the corresponding constant A is selected and fed to the second input of adder 18, where the value of y is formed) + 0.5 (2 (; + B () from the output of the adder 18; the value is received at the input of commutator 19. If the argument X has a positive sign, 9098 then in the first discharge of de register 14 is stored O and the value yd) is fed to the input of register 21 through switch 19 with a shift by one bit to the right, i.e. is normalized, and the value enters the second low-order input of the adder 17 through the element NOT 16. The first inputs of the register output adder 17c 12 receive the value of the integer part of the argument x. At the output of the adder 17, the value zy + 1 is formed. If the argument x has a negative sign, then the value 1, coming from the output of the first bit of register 14 to the control input of switch 19, allows the value y to pass (H from the output of adder 18 to the input of register 21 no shift, and the input of the low bit of the adder 17 through the element NOT 16 enters O. In this case, the output of the adder is 17. The order and the mantissa of the new argument x are entered in registers 1 and 2, in registers 4 and 5 - the values of z | and z 4 for the argument Xj, and in registers 8, 9 and 10 - the values , + B and K value of the most significant bits, respectively. In the fifth cycle, the order of the output number is entered into register 20, and the mantissa is entered into register 21. New argument Xj- is entered into registers 1 and 2, and 4, 5, 8, 9, 10, 12, 13, and 14 results of intermediate calculations over the numbers x, Xj, and x. Register 20 has a size of + 1 to prevent overflow of the adder 17.

Claims (1)

CONVEYOR DEVICE FOR POTENTIATING BINARY ARRAYS ARRANGEMENTS, containing an input order register, an input mantissa register, an output order register, an output mantissa register, two adders, a first memory block, the input of the mantissa of the device being connected to the information input of the input mantissa register, which differs from that that, in order to improve performance, eight registers, a shift block, a second memory block, a third adder, a quadrator, a switch, a synchronization block and an element NOT are introduced into it, and the input is of the order of the device is dined with the information input of the input register of order, the output of which is connected to the control input of the shear block, the information inputs of which are connected to the outputs (η-l) of the lower bits of the input register of the mantissa (where n is the number of bits of the input register of the mantissa), the output of the first bit of which is connected to the information inputs of the first bits of the first and second registers, the information outputs of the shift block are connected to the information inputs (n ~ 1) of the lower bits of the second register, the outputs of the K bits of which are connected to the address the inputs of the first memory block (where K is the number of senior bits of the second register), the output of the first memory block is connected to the first input of the first / adder, the second input of which is connected to the output of the second register, the outputs (f-1) of the lower bits of the shift block are connected to information inputs (£ -1) the least significant bits of the first register (where £ is the number of senior bits of the shift block), the output of the first register is connected to the information input of the third register, the output of the first. the adder is connected to the fourth register information input, the outputs of the second register bits are connected to the fifth register information inputs, the third register output is connected to the sixth register information input, the fourth register output is connected to the quad input, the output of which is connected to the seventh register information input, the output the fifth register is connected to the information input of the eighth register, the output of which is connected to the address input of the second memory block, the output of the sixth register is connected to the first input House second adder LSB second input of which through the element is not connected to the output of the eighth register of the first category, the seventh register output connected to the input of the first group with a shift on 6061611 ¹¹ nS '' ⁶ ”one bit towards the least significant bits of the third adder, the second group of inputs of which is connected to the outputs of the second memory block, the output of the first bit of the eighth register is connected to the control input of the switch, the first group of information inputs of which is connected to the output of the third adder, outputs which are connected to the information inputs of the second group with a shift of one bit towards the lower bits of the switch, the output of which is connected to the information input of the output register of the mantissa, the output of which connected to the output of the device mantissa, the output of the second adder is connected to the information input of the output order register, the output of which is connected to the device order output, the first input of the synchronization unit is connected to the device start input, the second input of the synchronization unit is connected to the device reset input, the first output of the synchronization unit mode connected to the read output of the device, the first output of the clock pulses of the synchronization unit is connected to the clock inputs of the input registers of the order and mantissa, the second output of the clock in the synchronization block is connected to the clock inputs of the first and second registers, the third output of the clock pulses of the synchronization block is connected to the clock inputs of the third, fourth and fifth registers, the fourth output of the clock pulses of the synchronization block is connected to the clock inputs of the sixth, seventh and eighth registers, the fifth output of the clock pulses of the synchronization block is connected to the clock inputs of the output registers of order and mantissa, the second output of the clock pulses of the synchronization unit is connected to the clock inputs, the first and second registers, the third output d, the clock of the synchronization block is connected to the clock inputs of the third, fourth and fifth registers, the fourth output of the clock pulses of the synchronization block is connected to the clock inputs of the sixth, seventh and eighth registers, the fifth output of the clock pulses of the clock block is connected to the clock inputs of the output registers of the order and mantissa, the second output of the synchronization block mode is connected to the output of the device record.