SU1208582A1 - Device for writing information in internal memory - Google Patents

Description

the register is connected to the outputs of the third decoder, the inputs of the group of the second register are connected to the outputs

The invention relates to memory devices and can be used to write information to a RAM.

The purpose of the invention is to expand the field of application due to the synchronized reception of binary data,

FIG. 1 shows a block diagram of the proposed device; in fig. 2 and 3 - timing charts of the device; in fig. 4 is a block diagram of a code converter.

The device contains a pulse generator 1, a counter 2, decoders 3-7, elements 8-11, input block 12, code converter 13, comparison block 14, element 15, switch 16 and registers 17 and 18. Positions 19-73 denote the connection outputs between the device nodes, and 74-81 the device inputs.

The converter 13 codes contains the element AND 82, the element NO 83, the counter 84, the element OR 85, the element AND 86, the trigger 87, the distributor, 88 pulses, the register 89, the decoder 90, the counter 91, the element 92, the element HE 93, the counter 94, element OR 95, element AND 96, trigger 97, register 98, decoder 99 and counter 100.

Unit 12 contains a circuit for polling the coding windings, a sensor code and an input button. The coordinate field of block 12 contains a zone of squares in which the numbers of data sources are depicted. Zones of squares are divided into eight lines according to the number of input information lines. The number of squares in a row is sixteen by the number of data sources connected to each information highway.

The outputs of register 17 are connected to the eight elements of the display by the number of inputs 74-81, and the outputs of the register 18 45 are connected to sixteen elements of the indication by the number of bits of the sequence 1208582

the second decoder, the outputs of the first and second registers are the outputs of the device.

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The device works as follows.

The generator 1 continuously generates pulses at the outputs 19 and 20. Under the influence of the pulses from the output 19, the counter 2 and the decoders 3-7 are continuously operated (timing diagrams in Figures 2 and 3). The device operates cyclically. At the beginning of each cycle, the code at outputs 21-36 of counter 2 is equal to O, and the first outputs 37, 45, 53, 57, and 59 of decoders 3-7 are equal to 1. At this time, at output 60 of element 8, a pulse is generated to be set to the original the state of the converter 13, then begins with polling the block 12 and converting the serial code at the output 63 of the block 12 into the parallel binary code at the outputs 64-67 and 68-71 of the converter 13. The control signal at the output 72 of the converter 13 is a sign of the correct conversion code. Converter 13 operates only at the moment of action of the pulses at the outputs 53-55 of the decoder 5 and of the executive pulses at the outputs 49-52 of the decoder 4. At the time of the action of the pulse at the output 53 of the decoder 5, a serial 2 / bit code and a parallel binary code of the coordinates X and U (exits 64 and 65 and 68 and 69). At the time of the pulse at the output 54 of the decoder 5, the unitary code is converted into the parallel binary code of the higher bits X (outputs 66 and 67), and at the moment of the pulse at the output 55 of the decoder 5, the unitary code is converted into the parallel binary code of the lower bits (exits 70 and 71).

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in the conversion of the 2-digit code X, the element is NOT 83, the trigger 87, the elements AND 82 and 86, the element OR 85, the counter 84.

The conversion of 2 bit code Y involves the element NOT 93, trigger 97, the elements AND .92 and 96, the element OR 95, the counter 94.

The transformation of the unitary code X takes part of the register 89, and the transformation of the unitary code Y occurs with the help of the register 98. The control signal 72 or 72 is removed from the outputs of the decoders 90 or 99.

The code at the outputs of the converter 13 is stored until the beginning of the next cycle of the device. Reception of information from data sources occurs when pulses are output at output 59 of decoder 7 and output 33 of counter 2. At that, the code value at outputs 29-32 of counter 2 determines the number of the data source connected to the information highway. Information is received from the first data source at the moment when the pulse arrives at the output 58 of the decoder 6, and at the very beginning of this pulse at the output 61 of the element I 9, a reset signal is generated for the registers 17 and 18.

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The information in the register 17 is recorded at the time of the pulse at the output 62 of the element I 10. The register 17 has eight information inputs and eight

There are 5 outputs, the number of rows of the coordinate field of block 12. Register 17 registers only a single signal of the first bit of the sequential code from each data source. Register 18 can record a sequential code from any (one of 128) data sources. Through the switch 16 passes the code only with one of

J5 inputs 74-81 corresponding to the eight-rows of the coordinate field of block 12. The selection of information highways is controlled by the code supplied to the control input of the commutator 16 from the outputs 68-70 of the converter 13, and the selection control of the sequential code from any (one of sixteen) a) data sources and the selected trunk are implemented using block 14. In order to output sequential information to the display elements coming from any data source, it is enough for the operator to combine the sensor codes of the block 12 with a square of the coordinate field of block 12, the number of which corresponds to the number of the selected data source.

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Claims (1)

DEVICE FOR RECORDING INFORMATION IN RAM, containing a pulse generator, the first output of which is connected to the input of the counter, the second output of the pulse generator is connected to the input of the first decoder, the group inputs of which are connected to the outputs of the first group of the counter, the outputs of the second and third groups of the counter are connected to the inputs, respectively the second and third decoders, the outputs of the fourth counter group are connected to the inputs of the fourth decoder group, the input of which is connected to the output of the fifth decoder, the inputs of which are connected to the outputs of the fifth group of the counter, the inputs of the first element And are connected to the first outputs of the first, second, third and fourth decoders, the inputs of the second element And are connected to the first outputs of the first, second and third decoders and to the second output of the fourth decoder, the inputs of the third element And are connected to the first inputs of the second and third decoders and to one of the outputs of the fourth counter group, the inputs of the fourth element And are connected to the second output of the first decoder and to the first output of the fourth decoder, you the course of the fourth element And is connected to the first input of the data input unit, the second input of which is connected to the third output of the first decoder, the inputs of the code converter are connected to the outputs of the third decoder, to the corresponding outputs of the second decoder, to the outputs of the second group of the counter, to the output of the first decoder and to the output of the data input unit, the outputs of the code converter are the outputs of the first group of the device, characterized in that, in order to expand the scope due to the synchronized reception of binary data x, it contains a comparison unit, registers, a fifth AND element, and a switch, the inputs of the first group of which are connected to the outputs of the first group of the code converter, the inputs of the first group of the comparison unit are connected to the outputs of the second group of the code converter, the inputs of the second group of the comparison unit are connected to the outputs the fourth group of the counter, the inputs of the fifth element AND are connected to the output of the comparison unit, to the output of the switch, to the output of the code converter and to one of the outputs of the first group of code converter, the first and second inputs of the first register connected to the outputs of the second and third elements, respectively, the inputs of the group of the first <·. the register and the inputs of the second group of the switch are the inputs of the device, the first and second inputs of the second register are connected to the outputs of the fifth and second elements And, the third and fourth inputs of the second register are connected to the outputs of the third decoder, the outputs of the first decoder, the inputs of the group and second registers are outputs — the second register is connected to the outputs of the device dams.