SU1288714A1 - Device for reducing matrix to triangular idempotent form - Google Patents

Abstract

The invention relates to the field of computer technology and is intended to solve systems of linear equations, determine the coefficients of a linear homogeneous difference equation, and determine the code of M-sequences. The purpose of the invention is to increase the speed of the device .. LliS 1C 00 00 sj

Description

The device contains an information input block 1, mxm binary matrix 2, memory block 3, memory cells 4, column selector block 5, rearranged with the first column, switch 6 of the inputs of memory cells 4 of the first column, second block 7 m elements AND, third block 8 ha of elements And, block 9 of control, block 10 of inverters, first block 11 elements And, element IL-NOT

one

. The invention relates to computing. It is intended to solve systems of linear equations, determine coefficients of a linear homogeneous difference equation, and determine the code of M-sequences. I

The purpose of the invention is to increase

speed.

Figure 1 shows a block diagram of a device for converting a matrix to a triangular idempotent form; Fig. 2 is a block diagram of a memory cell; FIG. 3 shows timing diagrams at the outputs of the control unit; Fig. 4 is a block diagram of the control unit; in FIG. 3, a column selection unit being swapped with the first column; figure 6 is an example of the implementation of the proposed device. A device for converting a matrix to a triangular idempotent form contains input information input unit 1, binary matrix 2, matrix 3, memory block 3, memory cells 4, column selector block 5 that is rearranged with the first column, switch 6 of the memory cells 4 of the first column , the second block 7 m elements And, the third block 8 w elements And, block 9 control, block 10 inverters, first block 11 And the element W-NOT 12, block 13 output solutions.

The memory cell 4 (FIG. 2) contains a switch 14, a memory element 15, an AND 16 element, an adder 17 modulo two, three information inputs 18-20, three control inputs 21-23, a recording input 24, a blocking input 25 , output 26 memory cells.

12, 13 decision output. The presence in the device of blocks 7 and 8 of elements I, of the switch of the inputs of the memory cells of the first column, and in the composition of each cell of the memory of the switch of inputs of the memory elements, makes it possible to reduce the matrix to a triangular idempotent form in 2 tons of time cycles (in prototype 3t cycles), which allowed to achieve the purpose of the invention. 6 Il.

The switch 14 is made in vchde element 2-2-2I-3 OR.

The control block 9 operates in accordance with the time diagrams obtained at the outputs 24, 21, 23,. 27 and 28 blocks (fig.Z). The control unit 9 (FIG. 4) comprises a clock pulse generator 29. Triggers 30-32, And -33 and 34 elements, a counter on m 35, trigger 36, the generator output 29 of clock pulses connected to a Bbw output 24 of control unit 9, the second trigger 21 of which is connected to the output of trigger 30. Forward and inverse the outputs of the trigger 32 through the elements And 33 and. 34 are connected respectively to the third 27 and fourth 23 outputs of the control unit 9, the fifth output 28 of which is connected to the output of the flip-flop 36.

The block 5 for selecting a column that is rearranged with the first column contains t-1 inverters 37, t-1 elements AND 38, inverters 39, t-1 elements AND 40, t-2 inverters 41, t-2 elements AND 42, element OR - NOT 43, t-1 of elements I 44, t-1 of elements IL 45,

element OR 46 (figure 5). I

The device works as follows.

At the initial moment, the memory cells 4 are set to the zero state, the flip-flops 30 and 32 of the block 9 are set to one, the flip-flops 31 and 36, the counter 35 of the block 9 to the zero state (the setting circuits are not shown). The trigger 30 is transferred to the zero state by the first pulse. 24 and forms impulse 21.

At the moment of action of the pulse at the first control input 21 from the outputs of the information input unit 1, cells 4 of the matrix memory are inputted at input 18 by the first pulse 24 a, defined for all 2, ..., t, and

memory cells 4 memory block 3 memory -

t-dimensional row vector b.

The back edge of the pulse 21, the trigger 31 is set to one state, and the elements 33 and 34 are opened at the first inputs, and the trigger 32 starts operating in the counting mode.

20

During the action of the first pulse at the third output 27 of the control unit 9, the potential at the inputs 23 and 25 is zero, and the signal at the outputs 26 of the memory cells 4 corresponds to the signal at the outputs of the data memory elements 15 of the memory cells 4, and at the inputs The column selection block 5, which is rearranged with the first column, receives signals from the outputs 25 26 of the memory cells 4 of the first row of the matrix 2 and from the outputs of the 26 diagonal cells 4 of the matrix. Block 5, which has m outputs, determines the column that needs to be rearranged with the first column according to the following principle: if on. output 26 of cell 4 of the memory of the first row of the first column of matrix 2 has a single potential

on the first output of block 5, on the 2nd outputs of block 5 a zero signal is generated. If the output 26 cells 4 memory of the first row of the first column

 0 | output diagonal cell 4 unit potentials are formed at the outputs of those elements 38, the inputs of which are connected to the outputs of these columns, while using inverters 39 and elements 40 forming a single potential only at the output of that element 40, the input of which through the element 38 is connected to the single output of the upper cell 4 and the zero output of the diagonal cell and the leftmost column, i.e. using the inverters 39 and AND elements 40, the most significant bit (the leftmost column) is selected. At the output of the element OR NOT 43, in this case there is a zero potential blocking the elements AND 44, and at the outputs of the elements OR 45 the unit potential takes place only at the output of that element OR which is connected to the unit output of the element 40 and corresponds to the number of the left column that is needed

thirty

rearrange with the first column. When., A single signal is formed by the absence of a 35 column with a single potential at the output of the upper cell 4 of the memory and with a zero potential at the output of the diagonal cell 4, the column of the leftmost matrix 2 is selected. There is a zero potential of the upper column, the single signal forms a “diagonal 4 memory cells, with

this at the output of the OR-NOT 43 element has a single potential, and with the help of inverters 41 and elements 45 AND 42, a single potential is formed only at the output of that element 42 that is directly connected to the leftmost column (single output of the top 50 cell 4 memories). This unit potential is transmitted through elements AND 44, LGS 45 and 46 to the first output of block 5 and to that output, the number of which corresponds to the leftmost one. If there is a single potential of 55 columns. Thus, during the output of the cell 4 of the first pulse memory at the output 27 of the block of the row of the first column, the unit signal has this signal first only at the outputs of block 7 (at the outputs of the elements 22), the number of which corresponds to the first output and the output of block 5, whose number corresponds to the number of the leftmost column of matrix 2, in which the outputs of the upper and diagonal memory cells 4 have unit and zero potentials respectively, and in the absence of Such a column produces a single signal at the output of block 5, the number of which corresponds to the number of the leftmost column of matrix 2, in which a single potential takes place at the output of the upper memory cell 4.

0

five

And 40, and also at the output of the element OR NOT 43, at the outputs of the elements OR 45, and, consequently, at the 2 outputs of block 5 there is a zero potential, and at the first output of block 5 there is a unit potential. At zero you-. During the upper cell 4 of the first column, when there are columns with a single output on the upper cell 4 and zero 0 | output in the diagonal cell 4, the unit potentials are formed at the outputs of those elements 38 that connect the inputs to these columns. tori 39 and elements 40, a single potential is formed only at the output of that element 40, whose input through element 38 is connected to the single output of the upper cell 4 and the zero output of the diagonal cell and the leftmost column, i.e. using the inverters 39 and AND elements 40, the most significant bit (the leftmost column) is selected. At the output of the element OR NOT 43, in this case there is a zero potential blocking the elements AND 44, and at the outputs of the elements OR 45 the unit potential takes place only at the output of that element OR which is connected to the single output of the element AND 40 and corresponds to the number of the leftmost column that is needed

0

first and selected leftmost columns. With the arrival of a pulse at the input 24 of the entry in the cells 4 of the memory of the first column of the matrix 2 and the first memory of the memory in block 3 of the memory, the information from the memory 4 of the column that corresponds to the selected left column, and A line-by-line census of information from the first column of matrix 2 and the first cell of memory block 3 is performed in this extreme left column. In the remaining cells 4 of the memory of the matrix 2 and of the memory 3, the information remains unchanged. If the top row of matrix 2 is zero (in the absence of the leftmost column of the matrix or the first column is the leftmost column), the information in all cells 4 of the memory remains unchanged in this cycle. During the operation of the first unit impulse, the third control inputs 23 of the memory cells 4, the outputs 27 and the second control inputs 22 have a zero potential, and the block 8 of the elements AND generates a potential only at the outputs whose numbers correspond to the column numbers matrices 2 (except the first), in which at the moment at the outputs 26 of the upper cells 4 of memory there is a single potential. In this case, cells 4 of the kth row of the 2nd column are modulo two summaries of the memory element 15 of this cell 4 of the memory with the output of cell 4 of the memory of the kth row of the first column, logically multiplied with the signal a blocking input 25 of this cell 4 memory.

With the arrival of a pulse at the input 24 of the record in the cells 4 of the memory, the third information inputs 20 record information from the outputs 26 of the other cells 4 of the memory in accordance with the production connections.

Thus, a single execution (the basic operations of the algorithm for bringing the matrix to a triangular idempotent form takes two time cycles, and the matrix is brought to a triangular idempotent form as a result of the w-multiple execution of the basic operations, i.e. cycle.

As a result of converting matrix 2 to a triangular idempotent form, memory block 3 contains the information of a certain string, which is one of the solutions of & systems of m linear equations with m unknowns of the form 13. b. After m times performing basic operations (when the counter 35 of the control unit 9 is controlled by m pulses 27) is calculated, a differential is formed at the output of the counter 35, setting the trigger 31 of the block 9 to the zero state and the trigger 36 to the single state. In this case, the first pulse from the output of the generator 29 of the block 9 triggers, the ger 36 returns to its initial state, and at the 28 of the control block 9 a decision output signal is generated, while the decision output in the block 13 is performed if there is no single signal at least one of the outputs of the block 11 elements And, i.e. in the presence of a single signal at the output of the element ШШ-НЕ 12.

An introduction to the known device to bring the matrix to a triangular idempotent form of the second, third blocks of AND elements, the switch of the inputs of the first column memory cells, and the composition of each cell of the switch of the inputs of the memory elements allows the matrix to be brought to triangular idempotent

form in 2 tons of time cycles, while in the known device this conversion was carried out in 3 tons of time cycles. This leads to a reduction in processing time by 1.5 times.

Claims (1)

Invention Formula A device for converting a matrix to a triangular idempotent form, which contains an input information input unit, a control unit, mxm binary matrix consisting of memory slots, a memory block consisting of m memory cells, an inverter block, an output block. the bora of the column rearranged with the first column, the first group of inputs of which is connected to the outputs of the memory cells of the first row of the matrix, the second group of inputs combined with the inputs of the block of the aei TopOB and connected to the outputs of the diagonal cells of the binary matrix, the first block of elements And, the element IL-NOT, the inputs of which are connected to the outputs 712 the first block of I elements, the first group of inputs of which is connected to the outputs of the inverter block, the decision output block whose information inputs are combined with the first group of inputs of the first block of I elements and connected to the outputs of the memory cells of the memory block, the outputs of the input block. input / information. are connected to the first information inputs of the binary matrix memory cells and the memory block, which include memory elements whose recording input is connected to the memory input of the memory cell, the I element whose first input is connected to the interlock the input of the memory cell, the modulo two adder, the first input of which is connected to the output of the memory element, and the second input is connected to the output of the AND element, which is characterized by the fact that, in order to improve speed, a second block of AND elements are entered into it, whose outputs are connected to the second control inputs of the memory cells of the corresponding columns of the binary matrix, the third block of elements I, the first input of the first group of inputs of which is connected to the zero potential bus, the first group of inputs connected to. outputs of 2 memory cells of the first row of the binary matrix, outputs of the third block of elements, and connect respectively in the blocking the inputs of the memory cells, the switch of the inputs of the memory cells of the first column, the control inputs of which are combined with the first inputs of the second block of elements And are connected to the outputs of the column selection block that is rearranged with the first column, each group of information inputs is connected to the outputs of the cells the memory of the corresponding row of the binary matrix and the memory block, the output of the switch of the inputs of the memory cells of the first column is connected to the second information input of the first cell of the corresponding row of the first column of the binary code the matrix and the first memory cell block of the memory, the first control unit output is connected to inputs of memory cells recording the binary matrix and a memory unit, the second output of the control unit is connected with the first yn 5 t 20 25 thirty 35 40 45 50 55 148 equal inputs of the binary matrix memory cells and the memory block, the third output of the control unit is connected to the second inputs of the second block elements, the fourth output of the control unit is connected to the third control inputs of the binary matrix memory cells and the second memory block elements And the third block, the fifth output of the control block is connected to the write input of the decision output block, whose blocking input is connected to the output of the OR-NOT element, the second information inputs of the memory cells of the row of 2 columns are connected to the output ci memory of the first column of the corresponding row, the third information input of the memory cell of the i-th row (i 1-m-1) of the j-ro column (j 1-m-1) of the binary matrix is connected to the output of the memory cell (1- " -1) -th row (J + 1) -th column of the binary matrix, the third information input of the memory cell of the i-th row of the m-th column of the binary matrix. Connected to the output of the memory cell (i + 1) -and row of the first column binary matrix, the third information input of the memory cell of the wth row of the j-ro column of the binary matrix is connected to the output of the memory cell of the first row () -ro of the column of the binary matrix, third information entry of the memory card) the m-th row of the nth column-binary matrix is connected to the output of the memory cell of the first row of the first column of the binary matrix; the third information input of the j-th memory cell of the memory block is connected to the output of (j + 1) -u cell memory of the block memory, the third information input of the tth memory cell of the memory block is connected to the output of the first memory cell of the memory block, and a switch is inserted into each memory cell, three information inputs of which are connected to the information inputs of the memory cell, three . the control inputs of the switch are connected to the control inputs of the memory cell, the second information input of the switch is connected to the second input of the AND element of the memory cell, and the output of the modulo two is connected to the output of the memory cell. 2 Fig.Z ) tacrrnllStr / n)) t1 SchP ShchGt 5) 1tp-3) W 18Vin} fy iy W & / e / F. (8 jjj20t-f () ())) ( / flT / X iB iW tw / yG / F ,, r „, ) () ()) (Gt () (2 {P , Bxoff pg g ucmp sddiga 2-m bit , : five ; OCF-CHff w j / Editor N. Bobkova Compiled by I. Pchelintsev Tehred L.Oleynik Proofreader L.Pilipenko Order 7810/48 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4